Datasheet

Data Sheet ADuC7124/ADuC7126
Rev. C | Page 103 of 108
09123-050
IO
V
DD
3.3
V
2.6V
2.41V TYP2.41V TYP
128ms TYP
LV
DD
POR
MRST
0.12ms TYP
POWER-ON RESET OPERATION
An internal power-on reset (POR) is implemented on the
ADuC7124/ADuC7126. For LV
DD
below 2.40 V typical, the
internal POR holds the part in reset. As LV
DD
rises above 2.41 V,
an internal timer times out for typically 128 ms before the part
is released from reset. The user must ensure that the power
supply, IOV
DD
, reaches a stable 2.7 V minimum level by this
time. Likewise, on power-down, the internal POR holds the part
in reset until LV
DD
drops below 2.40 V. Figure 69 illustrates the
operation of the internal POR in detail.
Figure 69. Internal Power-On Reset Operation