Datasheet

Data Sheet ADuC7124/ADuC7126
Rev. C | Page 11 of 108
Table 6. SPI Slave Mode Timing (Phase Mode = 1)
Parameter Description Min Typ Max Unit
t
CS
CS to SCLK edge
200 ns
t
SL
SCLK low pulse width (SPIDIV + 1) × t
HCLK
ns
t
SH
SCLK high pulse width (SPIDIV + 1) × t
HCLK
ns
t
DAV
Data output valid after SCLK edge 25 ns
t
DSU
Data input setup time before SCLK edge
1
1 × t
UCLK
ns
t
DHD
Data input hold time after SCLK edge
1
2 × t
UCLK
ns
t
DF
Data output fall time 5 12.5 ns
t
DR
Data output rise time 5 12.5 ns
t
SR
SCLK rise time 5 12.5 ns
t
SF
SCLK fall time 5 12.5 ns
t
SFS
CS
high after SCLK edge
0 ns
1
t
UCLK
= 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider.
09123-132
SCLK
(POLARITY = 0)
CS
SCLK
(POLARITY = 1)
t
SH
t
SL
t
SR
t
SF
t
SFS
MISO MSB BIT 6 TO BIT 1 LSB
MOSI MSB IN BIT 6 TO BIT 1 LSB IN
t
DHD
t
DSU
t
DAV
t
DR
t
DF
t
CS
Figure 5. SPI Slave Mode Timing (Phase Mode = 1)