Datasheet

ADuC7124/ADuC7126 Data Sheet
Rev. C | Page 14 of 108
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
DGND
LV
DD
IOV
DD
IOGND
P4.6/PLAO[14] P4.7/PLAO[15]
P0.6/T1/MRST/PLAO[3]
TCK
TDO
P3.0/PWM0/PLAI[8] P3.1/PWM1/PLAI[9]
P3.2/PWM2/PLAI[10]
P3.3/PWM3/PLAI[11]
P0.3/TRST/ADC
BUSY
P3.4/PWM4/PLAI[12] P3.5/PWM5/PLAI[13]
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
ADC3/CMP1 ADC2/CMP0 ADC1 ADC0 GND
REF
AGND AV
DD
DAC
REF
V
REF
RTCK P4.4/PLAO[12] P4.3/PLAO[11] P4.2/PLAO[10] P1.0/T1/SPM0/SIN0/I2C0SCL/PLAI[0] P1.1/SPM1/SOUT0/I2C0SDA/PLAI[1] P1.2/SPM2/RTS/I2C1SCL/PLAI[2]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
ADC4
ADC5
ADC6
ADC7
ADC8
ADC9
ADCNEG
DACGND
DACV
DD
DAC0/ADC12
DAC1/ADC13
TMS
TDI
XCLKO
XCLKI
BM/P0.0/CMP
OUT
/PLAI[7]
NC = NO CONNECT
P1.3/SPM3/CTS/I2C1SDA/PLAI[3]
P1.4/SPM4/RI/SPICLK/PLAI[4]/IRQ2
P1.5/SPM5/DCD/SPIMISO/PLAI[5]/IRQ3
P4.1/PLAO[9]/SOUT1
P4.0/PLAO[8]/SIN1
P1.6/SPM6/PLAI[6]
P1.7/SPM7/DTR/SPICS/PLAO[0]
P3.7/PWM
SYNC
/PLAI[15]
P3.6/PWM
TRIP
/PLAI[14]
IOV
DD
IOGND
P0.7/ECLK/XCLK/SPM8/PLAO[4]/SIN0
P2.0/SPM9/PLAO[5]/CONV
START
/SOUT0
IRQ1/P0.5/ADC
BUSY
/PLAO[2]
IRQ0/P0.4/PWM
TRIP
/PLAO[1]
RST
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
ADuC7124
TOP VIEW
(Not to Scale)
09123-107
NOTES
1. THE EXPOSED PADDLE MUST BE SOLDERED TO THE PCB TO ENSURE PROPER
HEAT DISSIPATION, NOISE, AND MECHANICAL STRENGTH BENEFITS.
Figure 7. ADuC7124 Pin Configuration
Table 9. Pin Function Descriptions (ADuC7124 64-Lead LFCSP)
Pin No. Mnemonic Description
0 Exposed Paddle Exposed Paddle. The LFCSP_VQ has an exposed paddle that must be left unconnected.
1 ADC4 Single-Ended or Differential Analog Input 4.
2 ADC5 Single-Ended or Differential Analog Input 5.
3 ADC6 Single-Ended or Differential Analog Input 6.
4 ADC7 Single-Ended or Differential Analog Input 7.
5 ADC8 Single-Ended or Differential Analog Input 8.
6 ADC9 Single-Ended or Differential Analog Input 9.
7 ADCNEG
Bias Point or Negative Analog Input of the ADC in Pseudo Differential Mode. Must be
connected to the ground of the signal to convert. This bias point must be between 0 V
and 1 V.
8 DACGND Ground for the DAC. Typically connected to AGND.
9 DACV
DD
3.3 V Power Supply for the DACs. Must be connected to AV
DD
.
10 DAC0/ADC12
DAC0 Voltage Output (DAC0).
Single-Ended or Differential Analog Input 12 (ADC12).
11 DAC1/ADC13
DAC1 Voltage Output (DAC1).
Single-Ended or Differential Analog Input 13 (ADC13).
12 TMS JTAG Test Port Input, Test Mode Select. Debug and download access.
13 TDI JTAG Test Port Input, Test Data In.