Datasheet

Data Sheet ADuC7124/ADuC7126
Rev. C | Page 15 of 108
Pin No. Mnemonic Description
14 XCLKO Output from the Crystal Oscillator Inverter.
15 XCLKI
Input to the Crystal Oscillator Inverter and Input to the Internal Clock Generator
Circuits.
16 BM/P0.0/CMP
OUT
/PLAI[7]
Multifunction I/O Pin.
Boot mode (BM). The ADuC7124 enters download mode if BM is low at reset and
executes code if BM is pulled high at reset through a 1 kΩ resistor.
General-Purpose Input and Output Port 0.0 (P0.0).
Voltage Comparator Output (CMP
OUT
)
Programmable Logic Array Input Element 7 (PLAI[7]).
17 DGND Ground for Core Logic.
18 LV
DD
2.6 V Output of the On-Chip Voltage Regulator. This output must be connected to a
0.47 µF capacitor to DGND only.
19 IOV
DD
3.3 V Supply for GPIO and Input of the On-Chip Voltage Regulator.
20 IOGND Ground for GPIO. Typically connected to DGND.
21 P4.6/PLAO[14]
General-Purpose Input and Output Port 4.6 (P4.6).
Programmable Logic Array Output Element 14 (PLAO[14]).
22 P4.7/PLAO[15]
General-Purpose Input and Output Port 4.7 (P4.7).
Programmable Logic Array Output Element 15 (PLAO[15]).
23 P0.6/T1/MRST/PLAO[3]
Multifunction Pin, Driven Low After Reset.
General-Purpose Output Port 0.6 (P0.6).
Timer1 Input (T1).
Power-On Reset Output (MRST).
Programmable Logic Array Output Element 3 (PLAO[3]).
24 TCK JTAG Test Port Input, Test Clock. Debug and download access.
25 TDO JTAG Test Port Output, Test Data Out.
26 P3.0/PWM0/PLAI[8]
General-Purpose Input and Output Port 3.0 (P3.0).
PWM Phase 0 (PWM0).
Programmable Logic Array Input Element 8 (PLAI[8]).
27 P3.1/PWM1/PLAI[9]
General-Purpose Input and Output Port 3.1 (P3.1).
PWM Phase 1 (PWM1).
Programmable Logic Array Input Element 9 (PLAI[9]).
28 P3.2/PWM2/PLAI[10]
General-Purpose Input and Output Port 3.2 (P3.2).
PWM Phase 2 (PWM2).
Programmable Logic Array Input Element 10 (PLAI[10]).
29 P3.3/PWM3/PLAI[11]
General-Purpose Input and Output Port 3.3 (P3.3).
PWM Phase 3 (PWM3).
Programmable Logic Array Input Element 11 (PLAI[11]).
30 P0.3/TRST/ADC
BUSY
General-Purpose Input and Output Port 0.3 (P0.3).
JTAG Test Port Input, Test Reset (TRST). JTAG reset input. Debug and download access. If
this pin is held low, JTAG access is not possible because the JTAG interface is held in reset
and P0.1/P0.2/P0.3 are configured as GPIO pins.
ADC
BUSY
Signal Output (ADC
BUSY
).
31 P3.4/PWM4/PLAI[12]
General-Purpose Input and Output Port 3.4 (P3.4).
PWM Phase 4 (PWM4).
Programmable Logic Array Input 12 (PLAI[12]).
32 P3.5/PWM5/PLAI[13]
General-Purpose Input and Output Port 3.5 (P3.5).
PWM Phase 5 (PWM5).
Programmable Logic Array Input Element 13 (PLAI[13]).
33
RST
Reset Input, Active Low.
34 IRQ0/P0.4/PWM
TRIP
/PLAO[1]
Multifunction I/O Pin.
External Interrupt Request 0, Active High (IRQ0).
General-Purpose Input and Output Port 0.4 (P0.4).
PWM Trip External Input (PWM
TRIP
).
Programmable Logic Array Output Element 1 (PLAO[1]).