Datasheet

Data Sheet ADuC7124/ADuC7126
Rev. C | Page 21 of 108
Pin No. Mnemonic Description
49 P2.3/SPM12/AE/SIN1
General-Purpose Input and Output Port 2.3 (P2.3).
Serial Port Multiplexed (SPM12).
External Memory Access Enable (AE).
UART1 Input (SIN1).
50
P2.1/WS
/PWM0/PLAO[6] General-Purpose Input and Output Port 2.1 (P2.1).
External Memory Write Strobe (WS
).
PWM Phase 0 (PWM0).
Programmable Logic Array Output Element 6 (PLAO[6]).
51
P2.2/RS
/PWM1/PLAO[7] General-Purpose Input and Output Port 2.2 (P2.2).
External Memory Read Strobe (RS
).
PWM Phase 1 (PWM1).
Programmable Logic Array Output Element 7 (PLAO[7]).
52 P3.6/AD6/PWM
TRIP
/PLAI[14]
General-Purpose Input and Output Port 3.6 (P3.6).
External Memory Interface (AD6).
PWM Safety Cutouff (PWM
TRIP
).
Programmable Logic Array Input Element 14 (PLAI[14]).
53 P3.7/AD7/PWM
SYNC
/PLAI[15]
General-Purpose Input and Output Port 3.7 (P3.7).
External Memory Interface (AD7).
PWM Synchronization (PWM
SYNC
).
Programmable Logic Array Input Element 15 (PLAI[15]).
54
P1.7/SPM7/DTR/SPICS
/PLAO[0] General-Purpose Input and Output Port 1.7 (P1.7).
Serial Port Multiplexed (SPM7).
Data Terminal Ready (DTR).
Chip Select (SPICS
).
Programmable Logic Array Output Element 0 (PLAO[0]).
55 P1.6/SPM6/PLAI[6]
General-Purpose Input and Output Port 1.6 (P1.6).
Serial Port Multiplexed (SPM6).
Programmable Logic Array Input Element 6 (PLAI[6]).
56 P4.0/SPM10/SIN1/AD8/PLAO[8]
General-Purpose Input and Output Port 4.0 (P4.0).
Serial Port Multiplexed (SPM10).
UART1 Input (SIN1).
External Memory Interface (AD8).
Programmable Logic Array Output Element 8 (PLAO[8]).
57 P4.1/SPM11/SOUT1/AD9/PLAO[9]
General-Purpose Input and Output Port 4.1 (P4.1).
Serial Port Multiplexed (SPM11).
UART1 Output (SOUT1).
External Memory Interface (AD9).
Programmable Logic Array Output Element 9 (PLAO[9]).
58 P1.5/SPM5/DCD/SPIMISO/PLAI[5]/IRQ3
General-Purpose Input and Output Port 1.5 (P1.5).
Serial Port Multiplexed (SPM5).
Data Carrier Detect (DCD).
Master Input, Slave Output (SPI MISO).
Programmable Logic Array Input Element 5 (PLAI[5]).
External Interrupt Request 3, Active High (IRQ3).
59 P1.4/SPM4/RI/SPICLK/PLAI[4]/IRQ2
General-Purpose Input and Output Port 1.4 (P1.4).
Serial Port Multiplexed (SPM4).
Ring Indicator (RI).
Serial Clock Input/Output (SPI SCLK).
Programmable Logic Array Input Element 4 (PLAI[4]).
External Interrupt Request 2, Active High (IRQ2).
60 P1.3/SPM3/CTS/I2C1SDA/PLAI[3]
General-Purpose Input and Output Port 1.3 (P1.3).
Serial Port Multiplexed (SPM3).
Clear to Send (CTS).
I2C1 (I2C1SDA).
Programmable Logic Array Input Element 3 (PLAI[3]).
61 P1.2/SPM2/RTS/I2C1SCL/PLAI[2]
General-Purpose Input and Output Port 1.2 (P1.2).
Serial Port Multiplexed (SPM2).
Ready to Send (RTS).
I2C1 (I2C1SCL).
Programmable Logic Array Input Element 2 (PLAI[2]).