Datasheet

ADuC7124/ADuC7126 Data Sheet
Rev. C | Page 40 of 108
on P0.5 (see the General-Purpose Input/Output section) if
enabled in the ADCCON register.
ADCDAT Register
Name: ADCDAT
Address: 0xFFFF0510
Default Value: 0x00000000
Access: Read only
ADCDAT is an ADC data result register that holds the 12-bit
ADC result, as shown in Figure 30.
ADCRST Register
Name: ADCRST
Address: 0xFFFF0514
Default Value: 0x00
Access: Read/write
ADCRST resets the digital interface of the ADC. Writing any value
to this register resets all the ADC registers to their default values.
ADCGN Register
Name: ADCGN
Address: 0xFFFF0530
Default Value: 0x0200
Access: Read/write
ADCGN is a 10-bit gain calibration register.
ADCOF Register
Name: ADCOF
Address: 0xFFFF0534
Default Value: 0x0200
Access: Read/write
ADCOF is a 10-bit offset calibration register.
CONVERTER OPERATION
The ADC incorporates a successive approximation (SAR)
architecture involving a charge-sampled input stage. This
architecture can operate in three different modes: differential,
pseudo differential, and single-ended.
Differential Mode
The ADuC7124/ADuC7126 each contains a successive approx-
imation ADC based on two capacitive DACs. Figure 32 and
Figure 33 show simplified schematics of the ADC in acquisition
and conversion phases, respectively. The ADC comprises con-
trol logic, a SAR, and two capacitive DACs. In Figure 32 (the
acquisition phase), SW3 is closed and SW1 and SW2 are in
Position A. The comparator is held in a balanced condition, and
the sampling capacitor arrays acquire the differential signal on
the input.
09123-017
CAPACITIVE
DAC
CAPACITIVE
DAC
CONTROL
LOGIC
COMPARATOR
SW3
SW1
A
A
B
B
SW2
C
S
C
S
V
REF
AIN0
AIN11
MUX
CHANNEL+
CHANNEL–
Figure 32. ADC Acquisition Phase
When the ADC starts a conversion, as shown in Figure 33, SW3
opens, and then SW1 and SW2 move to Position B. This causes
the comparator to become unbalanced. Both inputs are discon-
nected once the conversion begins. The control logic and the
charge redistribution DACs are used to add and subtract fixed
amounts of charge from the sampling capacitor arrays to bring
the comparator back into a balanced condition. When the
comparator is rebalanced, the conversion is complete. The
control logic generates the ADC output code. The output
impedances of the sources driving the V
IN+
and V
IN–
pins must
be matched; otherwise, the two inputs have different settling
times, resulting in errors.
09123-018
CAPACITIVE
DAC
CAPACITIVE
DAC
CONTROL
LOGIC
COMPARATOR
SW3
SW1
A
A
B
B
SW2
C
S
C
S
V
REF
AIN0
AIN11
MUX
CHANNEL+
CHANNEL–
Figure 33. ADC Conversion Phase
Pseudo Differential Mode
In pseudo differential mode, Channel− is linked to the
ADCNEG pin of the ADuC7124/ADuC7126. In Figure 34,
ADCNEG is represented as V
IN−
. SW2 switches between A
(Channel−) and B (V
REF
). The ADCNEG pin must be connected
to ground or to a low voltage. The input signal on V
IN+
can then
vary from V
IN−
to V
REF
+ V
IN−
. Note that V
IN−
must be chosen so
that V
REF
+ V
IN−
do not exceed AV
DD
.
09123-019
CAPACITIVE
DAC
CAPACITIVE
DAC
CONTROL
LOGIC
COMPARATOR
SW3
SW1
A
A
B
B
SW2
C
S
C
S
V
REF
AIN0
AIN11
V
IN–
MUX
CHANNEL+
CHANNEL–
Figure 34. ADC in Pseudo Differential Mode