Datasheet

Data Sheet ADuC7124/ADuC7126
Rev. C | Page 47 of 108
Table 54. FEExMOD MMR Bit Descriptions
Bit Description
[7:5] Reserved.
4 Flash/EE interrupt enable.
Set by the user to enable the Flash/EE interrupt. The interrupt occurs when a command is complete.
Cleared by the user to disable the Flash/EE interrupt.
3 Erase/write command protection.
Set by the user to enable the erase and write commands.
Cleared to protect the Flash/EE memory against the erase/write command.
2 Reserved. Should always be set to 0 by the user.
[1:0] Flash/EE wait states. Both Flash/EE blocks must have the same wait state value for any change to take effect.
Table 55. Command Codes in FEExCON
Code Command Description
0x00
1
Null Idle state.
0x01
1
Single read Load FEExDAT with the 16-bit data indexed by FEExADR.
0x02
1
Single write Write FEExDAT at the address pointed to by FEExADR. This operation takes 50 µs.
0x03
1
Erase/write
Erase the page indexed by FEExADR and write FEExDAT at the location pointed to by FEExADR. This operation
takes 20 ms.
0x04
1
Single verify
Compare the contents of the location pointed to by FEExADR to the data in FEExDAT. The result of the
comparison is returned in FEExSTA, Bit 1.
0x05
1
Single erase Erase the page indexed by FEExADR.
0x06
1
Mass erase
Erase user space. The 2 kB of kernel are protected in Block 0. This operation takes 2.48 sec. To prevent accidental
execution, a command sequence is required to execute this instruction.
0x07 Reserved Reserved.
0x08 Reserved Reserved.
0x09 Reserved Reserved.
0x0A Reserved Reserved.
0x0B Signature Gives a signature of the 64 kB of Flash/EE in the 24-bit FEExSIGN MMR. This operation takes 32,778 clock cycles.
0x0C Protect
This command can be run only once. The value of FEExPRO is saved and can be removed only with a mass erase
(0x06) or with the key.
0x0D Reserved Reserved.
0x0E Reserved Reserved.
0x0F Ping No operation, interrupt generated.
1
The FEExCON register always reads 0x07 immediately after execution of any of these commands.