Datasheet

Data Sheet ADuC7124/ADuC7126
Rev. C | Page 51 of 108
OTHER ANALOG PERIPHERALS
DAC
The ADuC7124/ADuC7126 incorporate two, or four, 12-bit
voltage output DACs on chip, depending on the model. Each
DAC has a rail-to-rail voltage output buffer capable of driving
5 kΩ/100 pF.
Each DAC has three selectable ranges: 0 V to V
REF
(internal
band gap 2.5 V reference), 0 V to DAC
REF
, and 0 V to AV
DD
.
DAC
REF
is equivalent to an external reference for the DAC.
The signal range is 0 V to AV
DD
.
MMRs Interface
Each DAC is independently configurable through a control
register and a data register. These two registers are identical for
the four DACs. Only DAC0CON (see Table 63) and DAC0DAT
(see Table 65) are described in detail in this section.
Table 62. DACxCON Registers
Name Address Default Value Access
DAC0CON 0xFFFF0600 0x00 R/W
DAC1CON 0xFFFF0608 0x00 R/W
DAC2CON 0xFFFF0610 0x00 R/W
DAC3CON 0xFFFF0618 0x00 R/W
Table 63. DAC0CON MMR Bit Descriptions
Bit Value Name Description
[7:6] Reserved.
5 DACCLK DAC update rate.
Set by the user to update the DAC
using Timer1.
Cleared by the user to update the
DAC using HCLK (core clock).
4 DACCLR DAC clear bit.
Set by the user to enable normal
DAC operation.
Cleared by the user to reset the data
register of the DAC to 0.
3 Reserved. This bit should be left at 0.
2 Reserved. This bit should be left at 0.
[1:0] DAC range bits.
00
Power-down mode. The DAC output
is in tristate.
01 0 V to DAC
REF
range.
10 0 V to V
REF
(2.5 V) range.
11 0 V to AV
DD
range.
Table 64. DACxDAT Registers
Name Address Default Value Access
DAC0DAT 0xFFFF0604 0x00000000 R/W
DAC1DAT 0xFFFF060C 0x00000000 R/W
DAC2DAT 0xFFFF0614 0x00000000 R/W
DAC3DAT 0xFFFF061C 0x00000000 R/W
Table 65. DAC0DAT MMR Bit Descriptions
Bit Description
[31:28] Reserved.
[27:16] 12-bit data for DAC0.
[15:0] Reserved.
Using the DACs
The on-chip DAC architecture consists of a DAC resistor string
followed by an output buffer amplifier. The functional equivalent
is shown in Figure 41.
09123-023
R
R
R
R
R
DAC0
V
REF
AV
DD
DAC
REF
Figure 41. DAC Structure
As illustrated in Figure 41, the reference source for each DAC is
user selectable in software. It can be either AV
DD
, V
REF
, or DAC
REF
.
In 0 V-to-AV
DD
mode, the DAC output transfer function spans
from 0 V to the voltage at the AV
DD
pin. In 0 V-to-DAC
REF
mode,
the DAC output transfer function spans from 0 V to the voltage at
the DAC
REF
pin. In 0 V-to-V
REF
mode, the DAC output transfer
function spans from 0 V to the internal 2.5 V reference, V
REF
.
The DAC output buffer amplifier features a true, rail-to-rail
output stage implementation. This means that, when unloaded,
each output is capable of swinging to within less than 5 mV of
both AV
DD
and ground. Moreover, the DAC linearity specification
(when driving a 5 k resistive load to ground) is guaranteed
through the full transfer function except the 0 to 100 codes,
and, in 0 V-to-AV
DD
mode only, Code 3995 to Code 4095.
Linearity degradation near ground and V
DD
is caused by satu-
ration of the output amplifier, and a general representation of its
effects (neglecting offset and gain error) is illustrated in Figure 42.
The dotted line in Figure 42 indicates the ideal transfer function,
and the solid line represents what the transfer function may
look like with endpoint nonlinearities due to saturation of the
output amplifier. Note that Figure 42 represents a transfer function
in 0 V-to-AV
DD
mode only. In 0 V-to-V
REF
or 0 V-to-DAC
REF
mode (with V
REF
< AV
DD
or DAC
REF
< AV
DD
), the lower nonlinear-
ity is similar. However, the upper portion of the transfer function
follows the ideal line right to the end (V
REF
in this case, not AV
DD
),
showing no signs of endpoint linearity errors.