Datasheet

Data Sheet ADuC7124/ADuC7126
Rev. C | Page 57 of 108
Table 77. POWCON1 MMR Bit Descriptions
1
Bit Value Name Description
[15:12] Reserved.
11 1 PWMPO
Clearing this bit powers
down the PWM. Always
clear to 00.
[10:9] 00 PWMCLKDIV
8 SPIPO
Clearing this bit powers
down the SPI.
[7:6] SPICLKDIV
SPI block driving clock
divider bits.
00 41.78 MHz.
01 20.89 MHz.
10 10.44 MHz.
11 5.22 MHz.
5 I2C1PO
Clearing this bit powers
down I2C1.
[4:3] I2C1CLKDIV
I2C0 block driving clock
divider bits.
00 41.78 MHz.
01 10.44 MHz.
10 5.22 MHz.
11 1.31 MHz.
2 I2C0PO
Clearing this bit powers
down I2C0.
[1:0] I2C0CLKDIV
I2C1 block driving clock
divider bits.
00 41.78 MHz.
01 10.44 MHz.
10 5.22 MHz.
11 1.31 MHz.
The POWCON1 write sequence is as follows:
1. Write Code 0x76 to Register POWKEY3.
2. Write user value to Register POWCON1.
3. Write Code 0xB1 to Register POWKEY4.
1
Divided clock for SPI/I2C0/I2C1 must be greater than or equal to the CPU clock
as selected by POWCON0 [2:0].