Datasheet

ADuC7124/ADuC7126 Data Sheet
Rev. C | Page 58 of 108
DIGITAL PERIPHERAL
GENERAL-PURPOSE INPUT/OUTPUT
The ADuC7124/ADuC7126 provide 40 general-purpose, bidirec-
tional I/O (GPIO) pins. All I/O pins are 5 V tolerant, meaning
the GPIOs support an input voltage of 5 V.
In general, many of the GPIO pins have multiple functions (see
the Pin Configurations and Function Descriptions section for
pin function definitions). By default, the GPIO pins are configured
in GPIO mode.
All GPIO pins have an internal pull-up resistor (of about 100 kΩ),
and their drive capability is 1.6 mA. Note that a maximum of
20 GPIOs can drive 1.6 mA at the same time. Using the GPxPAR
registers, it is possible to enable/disable the pull-up resistors for
the following ports: P0.0, P0.4, P0.5, P0.6, P0.7, and the eight
GPIOs of P1.
The 40 GPIOs are grouped in five ports, Port 0 to Port 4 (Port x).
Each port is controlled by four or five MMRs.
Note that the kernel changes P0.6 from its default configuration
at reset (MRST) to GPIO mode. If MRST is used for external
circuitry, an external pull-up resistor should be used to ensure
that the level on P0.6 does not drop when the kernel switches
mode. Otherwise, P0.6 goes low for the reset period. For example,
if MRST is required for power-down, it can be reconfigured in
GP0CON MMR.
The input level of any GPIO can be read at any time in the
GPxDAT MMR, even when the pin is configured in a mode
other than GPIO. The PLA input is always active.
When the ADuC7124/ADuC7126 enter a power-saving mode,
the GPIO pins retain their state. Also, note that, by setting
RSTCFG Bit 0, the GPIO pins can retain their state during a
watchdog or software reset.
Table 78. GPIO Pin Function Descriptions
Configuration
Port Pin 00 01 10 11
0 BM/P0.0 GPIO CMP MS0 PLAI[7]
TDI/P0.1
1
GPIO/JTAG PWM4 BLE
5
TDO/P0.2
1
GPIO/JTAG PWM5 BHE
5
TRST/P0.3
1
GPIO/JTAG TRST A16
5
ADC
BUSY
P0.4 GPIO/IRQ0 PWM
TRIP
MS1
5
PLAO[1]
P0.5 GPIO/IRQ1 ADC
BUSY
MS2
5
PLAO[2]
P0.6 GPIO MRST MS3
5
PLAO[3]
P0.7 GPIO ECLK/XCLK
2
SIN0 PLAO[4]
1 P1.0 GPIO/T1 SIN0 SCL0
3
PLAI[0]
P1.1 GPIO SOUT0 SDA0
3
PLAI[1]
P1.2 GPIO RTS
3
SCL1
3
PLAI[2]
P1.3 GPIO CTS
3
SDA1
3
PLAI[3]
P1.4 GPIO/IRQ2 RI
3
SCLK
3
PLAI[4]
P1.5 GPIO/IRQ3 DCD
3
MISO
3
PLAI[5]
P1.6 GPIO DSR
3
MOSI
3
PLAI[6]
P1.7 GPIO DTR
3
CS
3
PLAO[0]
2 P2.0 GPIO CONV
START
4
SOUT0 PLAO[5]
P2.1 GPIO PWM0 WS
5
PLAO[6]
P2.2 GPIO PWM1 RS
5
PLAO[7]
P2.3 GPIO AE
5
SIN1
P2.4 GPIO PWM0 MS0
5
SOUT1
P2.5 GPIO PWM1 MS1
5
P2.6 GPIO PWM2 MS2
5
P2.7 GPIO PWM3 MS3
5
3 P3.0 GPIO PWM0 AD0
5
PLAI[8]
P3.1 GPIO PWM1 AD1
5
PLAI[9]
P3.2 GPIO PWM2 AD2
5
PLAI[10]
P3.3 GPIO PWM3 AD3
5
PLAI[11]
P3.4 GPIO PWM4 AD4
5
PLAI[12]
P3.5 GPIO PWM5 AD5
5
PLAI[13]
P3.6 GPIO PWM
TRIP
AD6
5
PLAI[14]
P3.7 GPIO PWM
SYNC
AD7
5
PLAI[15]
4 P4.0 GPIO SIN1 AD8
5
PLAO[8]
P4.1 GPIO SOUT1 AD9
5
PLAO[9]
P4.2 GPIO AD10
5
PLAO[10]
P4.3 GPIO AD11
5
PLAO[11]
P4.4 GPIO AD12
5
PLAO[12]
P4.5 GPIO/RTCK AD13
5
PLAO[13]
P4.6 GPIO AD14
5
PLAO[14]
P4.7 GPIO AD15
5
PLAO[15]
1
These pins should not be used by user code .
2
When configured in Mode 1, P0.7 is ECLK by default, or core clock output. To
configure it as a clock input, the MDCLK bits in PLLCON must be set to 11.
3
See Table 90 for SPM configurations.
4
The
CONV
START
signal is active in all modes of P2.0.
5
External Memory Interface signals are only available on ADuC7126.