Datasheet

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Data Sheet ADuC7124/ADuC7126

Rev. C | Page 67 of 108

SPI Registers

The following MMR registers control the SPI interface: SPISTA, SPIRX, SPITX, SPIDIV, and SPICON.

SPI Status Register

Name: SPISTA

Address: 0xFFFF0A00

Default Value: 0x0000

Access: Read only

Function: This 32-bit MMR contains the status of the SPI interface in both master and slave modes.

Table 100. SPISTA MMR Bit Descriptions

Bit Name Description

[15:12] Reserved.

11 SPIREX

SPI Rx FIFO excess bytes present. This bit is set when there are more bytes in the Rx FIFO than indicated in the

SPIMDE bits in SPICON

This bit is cleared when the number of bytes in the FIFO is equal to or less than the number in SPIMDE.

[10:8] SPIRXFSTA[2:0] SPI Rx FIFO status bits.

[000] = Rx FIFO is empty.

[001] = one valid byte in the FIFO.

[010] = two valid bytes in the FIFO.

[011] = three valid bytes in the FIFO.

[100] = four valid bytes in the FIFO.

7 SPIFOF SPI Rx FIFO overflow status bit.

Set when the Rx FIFO was already full when new data was loaded to the FIFO. This bit generates an interrupt

except when SPIRFLH is set in SPICON.

Cleared when the SPISTA register is read.

6 SPIRXIRQ SPI Rx IRQ status bit.

Set when a receive interrupt occurs. This bit is set when SPITMDE in SPICON is cleared and the required

number of bytes has been received.

Cleared when the SPISTA register is read.

SPITXIRQ SPI Tx IRQ status bit.

Set when a transmit interrupt occurs. This bit is set when SPITMDE in SPICON is set and the required number

of bytes has been transmitted.

Cleared when the SPISTA register is read.

4 SPITXUF SPI Tx FIFO underflow.

This bit is set when a transmit is initiated without any valid data in the Tx FIFO. This bit generates an interrupt

except when SPITFLH is set in SPICON.

Cleared when the SPISTA register is read.

[3:1] SPITXFSTA[2:0] SPI Tx FIFO status bits.

[000] = Tx FIFO is empty.

[001] = one valid byte in the FIFO.

[010] = two valid bytes in the FIFO.

[011] = three valid bytes in the FIFO.

[100] = four valid bytes in the FIFO.

0 SPIISTA SPI interrupt status bit.

Set to 1 when an SPI-based interrupt occurs.

Cleared after reading SPISTA.