Datasheet

Data Sheet ADuC7124/ADuC7126
Rev. C | Page 69 of 108
Bit Name Description
9 SPIOEN Slave MISO output enable bit.
Set this bit for MISO to operate as normal.
Clear this bit to disable the output driver on the MISO pin. The MISO pin is open-drain when this bit is cleared.
8 SPIROW SPIRX overflow overwrite enable.
Set by the user, the valid data in the SPIRX register is overwritten by the new serial byte received.
Cleared by the user, the new serial byte received is discarded.
7 SPIZEN SPI transmits zeros when Tx FIFO is empty.
Set this bit to transmit 0x00 when there is no valid data in the Tx FIFO.
Clear this bit to transmit the last transmitted value when there is no valid data in the Tx FIFO.
6 SPITMDE SPI transfer and interrupt mode.
Set by the user to initiate transfer with a write to the SPITX register. Interrupt occurs only when SPITX is empty.
Cleared by the user to initiate transfer with a read of the SPIRX register. Interrupt occurs only when SPIRX is full.
5 SPILF LSB first transfer enable bit.
Set by the user, the LSB is transmitted first.
Cleared by the user, the MSB is transmitted first.
4 SPIWOM SPI wire-OR’ed mode enable bit.
Set to 1 enable open-drain data output. External pull-ups required on data output pins.
Cleared for normal output levels.
Serial clock polarity mode bit.
Set by the user, the serial clock idles high.
3 SPICPO
Cleared by the user, the serial clock idles low.
2 SPICPH Serial clock phase mode bit.
Set by the user, the serial clock pulses at the beginning of each serial bit transfer.
Cleared by the user, the serial clock pulses at the end of each serial bit transfer.
1 SPIMEN Master mode enable bit.
Set by the user to enable master mode.
Cleared by the user to enable slave mode.
0 SPIEN SPI enable bit.
Set by the user to enable the SPI.
Cleared by the user to disable the SPI.