Datasheet

ADuC7124/ADuC7126 Data Sheet
Rev. C | Page 72 of 108
I
2
C Master Status Register
Name: I2C0MSTA, I2C1MSTA
Address: 0xFFFF0804, 0xFFFF0904
Default Value: 0x0000, 0x0000
Access: Read only
Function: This 16-bit MMR is the I
2
C status register in master mode.
Table 103. I2CxMSTA MMR Bit Descriptions
Bit Name Description
[15:11] Reserved.
10 I2CBBUSY I
2
C bus busy status bit.
This bit is set to 1 when a start condition is detected on the I
2
C bus.
This bit is cleared when a stop condition is detected on the bus.
9 I2CMRxFO Master Rx FIFO overflow.
This bit is set to 1 when a byte is written to the Rx FIFO when it is already full.
This bit is cleared in all other conditions.
8 I2CMTC I
2
C transmission complete status bit.
This bit is set to 1 when a transmission is complete between the master and the slave it was
communicating with.
If the I2CMCENI bit in I2CxMCON is set, an interrupt is generated when this bit is set.
Clear this bit to clear the interrupt source.
7 I2CMNA I
2
C master NACK data bit.
This bit is set to 1 when a NACK condition is received by the master in response to a data write transfer.
If the I2CNACKENI bit in I2CxMCON is set, an interrupt is generated when this bit is set.
This bit is cleared in all other conditions.
6 I2CMBUSY I
2
C master busy status bit.
Set to 1 when the master is busy processing a transaction.
Cleared if the master is ready or if another master device has control of the bus.
5 I2CAL I
2
C arbitration lost status bit.
This bit is set to 1 when the I
2
C master is unable to gain control of the I
2
C bus.
If the I2CALENI bit in I2CxMCON is set, an interrupt is generated when this bit is set.
This bit is cleared in all other conditions.
I2CMNA I
2
C master NACK address bit.
This bit is set to 1 when a NACK condition is received by the master in response to an address.
If the I2CNACKENI bit in I2CxMCON is set, an interrupt is generated when this bit is set.
4
This bit is cleared in all other conditions.
3 I2CMRXQ I
2
C master receive request bit.
This bit is set to 1 when data enters the Rx FIFO. If the I2CMRENI in I2CxMCON is set, an interrupt is
generated.
This bit is cleared in all other conditions.
2 I2CMTXQ I
2
C master transmit request bit.
This bit goes high if the Tx FIFO is empty or contains only one byte and the master has transmitted an
address + write. If the I2CMTENI bit in I2CxMCON is set, an interrupt is generated when this bit is set.
This bit is cleared in all other conditions.
[1:0] I2CMTFSTA I
2
C master Tx FIFO status bits.
00 = I
2
C master Tx FIFO empty.
01 = one byte in master Tx FIFO.
10 = one byte in master Tx FIFO.
11 = I
2
C master Tx FIFO full.