Datasheet

ADuC7124/ADuC7126 Data Sheet
Rev. C | Page 74 of 108
I
2
C Address 1 Register
Name: I2C0ADR1, I2C1ADR1
Address: 0xFFFF081C, 0xFFFF091C
Default Value: 0x00
Access: Read/write
Function: This 8-bit MMR is used in 10-bit addressing
mode only. This register contains the least
significant byte of the address.
Table 107. I2CxADR1 MMR in 10-Bit Address Mode
Bit Name Description
[7:0] I2CLADR
These bits contain ADDR[7:0] in 10-bit
addressing mode.
I
2
C Master Clock Control Register
Name: I2C0DIV, I2C1DIV
Address: 0xFFFF0824, 0xFFFF0924
Default Value: 0x1F1F
Access: Read/write
Function: This MMR controls the frequency of the I
2
C
clock generated by the master on to the SCL
pin. For further details, see the I
2
C section.
Table 108. I2CxDIV MMR
Bit Name Description
[15:8] DIVH
These bits control the duration of the high
period of SCL.
[7:0] DIVL
These bits control the duration of the low
period of SCL.
I
2
C Slave Registers
I
2
C Slave Control Register
Name: I2C0SCON, I2C1SCON
Address: 0xFFFF0828, 0xFFFF0928
Default Value: 0x0000
Access: Read/write
Function: This 16-bit MMR configures the I
2
C
peripheral in slave mode.
Table 109. I2CxSCON MMR Bit Descriptions
Bit Name Description
[15:11] Reserved.
10 I2CSTXENI Slave transmit interrupt enable bit.
Set this bit to enable an interrupt after a slave transmits a byte.
Clear this interrupt source.
9 I2CSRXENI Slave receive interrupt enable bit.
Set this bit to enable an interrupt after the slave receives data.
Clear this interrupt source.
8 I2CSSENI I
2
C stop condition detected interrupt enable bit.
Set this bit to enable an interrupt on detecting a stop condition on the I
2
C bus.
Clear this interrupt source.
7 I2CNACKEN I
2
C NACK enable bit.
Set this bit to NACK the next byte in the transmission sequence.
Clear this bit to let the hardware control the ACK/NACK sequence.
6 I2CSSEN I
2
C slave SCL stretch enable bit.
Set this bit to 1 to enable clock stretching. When SCL is low, setting this bit forces the device to hold SCL low
until I2CSSEN is cleared. If SCL is high, setting this bit forces the device to hold SCL low after the next falling
edge.
Clear this bit to disable clock stretching.