Datasheet

Data Sheet ADuC7124/ADuC7126
Rev. C | Page 75 of 108
Bit Name Description
5 I2CSETEN I
2
C early transmit interrupt enable bit.
Setting this bit enables a transmit request interrupt just after the positive edge of SCL during the read bit
transmission.
Clear this bit to enable a transmit request interrupt just after the negative edge of SCL during the read bit
transmission.
4 I2CGCCLR I
2
C general call status and ID clear bit.
Writing a 1 to this bit clears the general call status (I2CGC) and ID (I2CGCID[1:0]) bits in the I2CxSSTA register.
Clear this bit at all other times.
I2CHGCEN I
2
C hardware general call enable.
When this bit and Bit 2 are set, and having received a general call (Address 0x00) and a data byte, the device
checks the contents of the I2CxALT against the receive register. If the contents match, the device has received a
hardware general call. This is used if a device needs urgent attention from a master device without knowing
which master it needs to turn to. This is a broadcast message to all master devices on the bus. The ADuC7124/
ADuC7126 watch for these addresses. The device that requires attention embeds its own address into the
message. All masters listen, and the one that can handle the device contacts its slave and acts appropriately.
The LSB of the I2CxALT register should always be written to 1, as per the I
2
C January 2000 bus specification.
Set this bit and I2CGCEN to enable hardware general call recognition in slave mode.
3
Clear this bit to disable recognition of hardware general call commands.
2 I2CGCEN I
2
C general call enable.
Set this bit to enable the slave device to acknowledge an I
2
C general call, Address 0x00 (write). The device then
recognizes a data bit. If it receives a 0x06 (reset and write programmable part of the slave address by hard-
ware) as the data byte, the I
2
C interface resets as per the I
2
C January 2000 bus specification. This command can
be used to reset an entire I
2
C system. If it receives a 0x04 (write programmable part of the slave address by
hardware) as the data byte, the general call interrupt status bit sets on any general call.
The user must take corrective action by reprogramming the device address.
Set this bit to allow the slave ACK I
2
C general call commands.
Clear this bit to disable recognition of general call commands.
1 ADR10EN I
2
C 10-bit address mode.
Set to 1 to enable 10-bit address mode.
Clear to 0 to enable normal address mode.
0 I2CSEN I
2
C slave enable bit.
Set by the user to enable I
2
C slave mode.
Clear this bit to disable I
2
C slave mode.
I
2
C Slave Status Registers
Name: I2C0SSTA, I2C1SSTA
Address: 0xFFFF082C, 0xFFFF092C
Default Value: 0x0000, 0x0000
Access: Read only
Function: This 16-bit MMR is the I
2
C status register in slave mode.
Table 110. I2CxSSTA MMR Bit Descriptions
Bit Name Description
15 Reserved.
14 I2CSTA
This bit is set to 1 if a start condition followed by a matching address is detected, a start byte (0x01) is
received, or general calls are enabled and a general call code of (0x00) is received.
This bit is cleared on receiving a stop condition.
13 I2CREPS This bit is set to 1 if a repeated start condition is detected.
This bit is cleared on receiving a stop condition.