Datasheet

ADuC7124/ADuC7126 Data Sheet
Rev. C | Page 76 of 108
Bit Name Description
[12:11] I2CID[1:0] I
2
C address matching register. These bits indicate which I2CxIDx register matches the received address.
[00] = received address matches I2CxID0.
[01] = received address matches I2CxID1.
[10] = received address matches I2CxID2.
[11] = received address matches I2CxID3.
10 I2CSS I
2
C stop condition after start detected bit.
This bit is set to 1 when a stop condition is detected after a previous start and matching address.
When the I2CSSENI bit in I2CxSCON is set, an interrupt is generated.
This bit is cleared by reading this register.
[9:8] I2CGCID[1:0] I
2
C general call ID bits.
[00] = no general call received.
[01] = general call reset and program address.
[10] = general program address.
[11] = general call matching alternative ID.
Note that these bits are not cleared by a general call reset command.
Clear these bits by writing a 1 to the I2CGCCLR bit in I2CxSCON.
7 I2CGC I
2
C general call status bit.
This bit is set to 1 if the slave receives a general call command of any type.
If the command received is a reset command, then all registers return to their default states.
If the command received is a hardware general call, the Rx FIFO holds the second byte of the command
and this can be compared with the I2CxALT register.
Clear this bit by writing a 1 to the I2CGCCLR bit in I2CxSCON.
6 I2CSBUSY I
2
C slave busy status bit.
Set to 1 when the slave receives a start condition.
Cleared by hardware if the received address does not match any of the I2CxIDx registers, the slave device
receives a stop condition, or a repeated start address does not match any of the I2CxIDx registers.
5 I2CSNA I
2
C slave NACK data bit.
This bit is set to 1 when the slave responds to a bus address with a NACK. This bit is asserted if a NACK was
returned because there was no data in the Tx FIFO or the I2CNACKEN bit was set in the I2CxSCON register.
This bit is cleared in all other conditions.
4 I2CSRxFO Slave Rx FIFO overflow.
This bit is set to 1 when a byte is written to the Rx FIFO when it is already full.
This bit is cleared in all other conditions.
I2CSRXQ I
2
C slave receive request bit.
This bit is set to 1 when the slave Rx FIFO is not empty.
This bit causes an interrupt to occur when the I2CSRXENI bit in I2CxSCON is set.
3
The Rx FIFO must be read or flushed to clear this bit.
2 I2CSTXQ I
2
C slave transmit request bit.
This bit is set to 1 when the slave receives a matching address followed by a read.
If the I2CSETEN bit in I2CxSCON = 0, this bit goes high just after the negative edge of SCL during the read
bit transmission.
If the I2CSETEN bit in I2CxSCON = 1, this bit goes high just after the positive edge of SCL during the read
bit transmission.
This bit causes an interrupt to occur when the I2CSTXENI bit in I2CxSCON is set.
This bit is cleared in all other conditions.
1 I2CSTFE I
2
C slave FIFO underflow status bit.
This bit goes high if the Tx FIFO is empty when a master requests data from the slave. This bit is asserted at
the rising edge of SCL during the read bit.
This bit is cleared in all other conditions.
0 I2CETSTA I
2
C slave early transmit FIFO status bit.
If the I2CSETEN bit in I2CxSCON = 0, this bit goes high if the slave Tx FIFO is empty.
If the I2CSETEN bit in I2CxSCON = 1, this bit goes high just after the positive edge of SCL during the write
bit transmission.
This bit asserts once only for a transfer.
This bit is cleared after being read.