Datasheet

ADuC7124/ADuC7126 Data Sheet
Rev. C | Page 80 of 108
Table 114. PWM Output Selection, HMODE = 1
PWMCON0 MMR
1
PWM Outputs
2
ENA HOFF POINV DIR PWM0 PWM1 PWM2 PWM3
0 0 X X 1 1 1 1
X 1 X X 1 0 1 0
1 0 0 0 0 0 HS LS
1 0 0 1 HS LS 0 0
1 0 1 0 HS LS 1 1
1 0 1 1 1 1 HS LS
1
X = don’t care.
2
HS = high side, LS = low side.
On power-up, PWMCON0 defaults to 0x12 (HOFF = 1 and
HMODE = 1). All GPIO pins associated with the PWM are
configured in PWM mode by default (see Table 115).
Table 115. Compare Registers
Name Address Default Value Access
PWM0COM0 0xFFFF0F84 0x0000 R/W
PWM0COM1 0xFFFF0F88 0x0000 R/W
PWM0COM2 0xFFFF0F8C 0x0000 R/W
PWM1COM0 0xFFFF0F94 0x0000 R/W
PWM1COM1 0xFFFF0F98 0x0000 R/W
PWM1COM2 0xFFFF0F9C 0x0000 R/W
PWM2COM0 0xFFFF0FA4 0x0000 R/W
PWM2COM1 0xFFFF0FA8 0x0000 R/W
PWM2COM2 0xFFFF0FAC 0x0000 R/W
The PWM trip interrupt can be cleared by writing any value to
the PWMCLRI MMR. Note that, when using the PWM trip
interrupt, users should make sure that the PWM interrupt
has been cleared before exiting the ISR. This prevents
generation of multiple interrupts.
PWM Convert Start Control
The PWM can be configured to generate an ADC convert start
signal after the active low side signal goes high. There is a
programmable delay between the time that the low-side signal
goes high and the convert start signal is generated.
This is controlled via the PWMCON1 MMR. If the delay
selected is higher than the width of the PWM pulse, the
interrupt remains low.
Table 116. PWMCON1 MMR Bit Descriptions (Address =
0xFFFF0FB4; Default Value = 0x00)
Bit Value Name Description
7 CSEN
Set to 1 by the user to enable the PWM
to generate a convert start signal.
Cleared by user to disable the PWM
convert start signal.
CSD3
Convert start delay. Delays the convert
start signal by a number of clock
pulses.
CSD2
CSD1
CSD0
0000 Four clock pulses.
0001 Eight clock pulses.
0010 12 clock pulses.
0011 16 clock pulses.
0100 20 clock pulses.
0101 24 clock pulses.
0110 28 clock pulses.
0111 32 clock pulses.
1000 36 clock pulses.
1001 40 clock pulses.
1010 44 clock pulses.
1011 48 clock pulses.
1100 52 clock pulses.
1101 56 clock pulses.
1110 60 clock pulses.
[3:0]
1111 64 clock pulses.
When calculating the time from the convert start delay to the
start of an ADC conversion, the user must take account of
internal delays. The following example shows the case of a delay
of four clocks. One additional clock is required to pass the
convert start signal to the ADC logic. Once the ADC logic
receives the convert start signal, an ADC conversion begins on
the next ADC clock edge (see Figure 50).
UCLK
LOW SIDE
COUNT
PWM SIGNAL
S
IGNAL PASSED
TO ADC LOGIC
TO CONVST
09123-045
Figure 50. ADC Conversion