Datasheet

ADuC7124/ADuC7126 Data Sheet
Rev. C | Page 84 of 108
PROCESSOR REFERENCE PERIPHERALS
INTERRUPT SYSTEM
There are 25 interrupt sources on the ADuC7124/ADuC7126
that are controlled by the interrupt controller. All interrupts
are generated from the on-chip peripherals, except for the
software interrupt (SWI), which is programmable by the user.
The ARM7TDMI CPU core recognizes interrupts as one of
two types: a normal interrupt request (IRQ) and a fast interrupt
request (FIQ). All the interrupts can be masked separately.
The control and configuration of the interrupt system is
managed through a number of interrupt-related registers. The
bits in each IRQ and FIQ register represent the same interrupt
source as described in Table 126.
The ADuC7124/ADuC7126 contain a vectored interrupt control-
ler (VIC) that supports nested interrupts up to eight levels. The
VIC also allows the programmer to assign priority levels to all
interrupt sources. Interrupt nesting must be enabled by setting
the ENIRQN bit in the IRQCONN register. A number of extra
MMRs are used when the full-vectored interrupt controller is
enabled.
IRQSTA/FIQSTA should be saved immediately upon entering
the interrupt service routine (ISR) to ensure that all valid
interrupt sources are serviced.
Table 126. IRQ/FIQ MMRs Bit Descriptions
Bit Description Comments
0
All interrupts OR’ed
(FIQ only)
This bit is set if any FIQ is active.
1 Software interrupt
User programmable interrupt
source.
2 Timer0 General-Purpose Timer 0.
3 Timer1 General-Purpose Timer 1.
4
Timer2 or wake-up
timer
General-Purpose Timer 2 or
wake-up timer.
5
Timer3 or watchdog
timer
General-Purpose Timer 3 or
watchdog timer.
6 Flash Control 0
Flash controller for Block 0
interrupt.
7 Flash Control 1
Flash controller for Block 1
interrupt.
8 ADC ADC interrupt source bit.
9 UART0 UART0 interrupt source bit.
10 UART1 UART1 interrupt source bit.
11 PLL lock PLL lock bit.
12 I2C0 master IRQ I
2
C master interrupt source bit.
13 I2C0 slave IRQ I
2
C slave interrupt source bit.
14 I2C1 master IRQ I
2
C master interrupt source bit.
15 I2C1 slave IRQ I
2
C slave interrupt source bit.
16 SPI SPI interrupt source bit.
17 XIRQ0 (GPIO IRQ0 ) External Interrupt 0.
18 Comparator Voltage comparator source bit.
19 PSM Power supply monitor.
20 XIRQ1 (GPIO IRQ1) External Interrupt 1.
Bit Description Comments
21 PLA IRQ0 PLA Block 0 IRQ bit.
22 XIRQ2 (GPIO IRQ2 ) External Interrupt 2.
23 XIRQ3 (GPIO IRQ3) External Interrupt 3.
24 PLA IRQ1 PLA Block 1 IRQ bit.
25 PWM PWM trip interrupt source bit.
IRQ
The IRQ is the exception signal to enter the IRQ mode of the
processor. It services general-purpose interrupt handling of
internal and external events.
All 32 bits are logically OR’ed to create a single IRQ signal to the
ARM7TDMI core. Descriptions of the four 32-bit registers
dedicated to IRQ follow.
IRQSTA Register
IRQSTA is a read-only register that provides the current-enabled
IRQ source status (effectively a logic AND of the IRQSIG and
IRQEN bits). When set to 1, that source generates an active IRQ
request to the ARM7TDMI core. There is no priority encoder
or interrupt vector generation. This function is implemented in
software in a common interrupt handler routine.
IRQSTA Register
Name: IRQSTA
Address: 0xFFFF0000
Default Value: 0x00000000
Access: Read only
IRQSIG Register
IRQSIG reflects the status of the various IRQ sources. If a periph-
eral generates an IRQ signal, the corresponding bit in the
IRQSIG is set; otherwise, it is cleared. The IRQSIG bits clear
when the interrupt in the particular peripheral is cleared. All
IRQ sources can be masked in the IRQEN MMR. IRQSIG is
read only. This register should not be used in an interrupt
service routine for determining the source of an IRQ exception;
IRQSTA should only be used for this purpose.
IRQSIG Register
Name: IRQSIG
Address: 0xFFFF0004
Default Value: 0x00000000
Access: Read only