Datasheet

Data Sheet ADuC7124/ADuC7126
Rev. C | Page 89 of 108
FIQVEC Register
The FIQ interrupt vector register, FIQVEC, points to a memory
address containing a pointer to the interrupt service routine of
the currently active FIQ. This register should be read only when
an FIQ occurs and FIQ interrupt nesting has been enabled by
setting Bit 1 of the IRQCONN register.
Name: FIQVEC
Address: 0xFFFF011C
Default Value: 0x00000000
Access: Read only
Table 136. FIQVEC MMR Bit Descriptions
Bit Type
Initial
Value
Description
[31:23] R 0 Always read as 0.
[22:7] R/W 0 IRQBASE register value.
[6:2] 0
Highest priority source. This is a
value between 0 and 27,
representing the currently active
interrupt source. The interrupts are
listed in Table 126. For example, if
the highest currently active FIQ is
Timer2, then these bits are [00100].
[1:0] 0 Reserved.
FIQSTAN Register
If IRQCONN Bit 1 is asserted and FIQVEC is read, one of the
FIQSTAN[7:0] bits is asserted. The bit that asserts depends on
the priority of the FIQ. If the FIQ is of Priority 0, Bit 0 asserts, if
Priority 1, Bit 1 asserts, and so forth.
When a bit is set in this register all interrupts of that priority
and lower are blocked.
To clear a bit in this register, all bits of a higher priority must be
cleared first. It is possible to clear only one bit at a time. For
example, if this register is set to 0x09, then writing 0xFF
changes the register to 0x08 and writing 0xFF a second time
changes the register to 0x00.
Name: FIQSTAN
Address: 0xFFFF013C
Default Value: 0x00000000
Access: Read/write
Table 137. FIQSTAN MMR Bit Descriptions
Bit Name Description
31:8
Reserved. These bits are reserved and should
not be written to.
7:0
Setting this bit to 1 enables nesting of FIQ
interrupts. Clearing this bit means no nesting
or prioritization of FIQs is allowed.
External Interrupts and PLA interrupts
The ADuC7124/ADuC7126 provide up to four external
interrupt sources and two PLA interrupt sources. These
external interrupts can be individually configured as level or
rising/falling edge triggered.
To enable the external interrupt source or the PLA interrupt
source, the appropriate bit must first be set in the FIQEN or
IRQEN register. To select the required edge or level to trigger
on, the IRQCONE register must be appropriately configured.
To properly clear an edge-based external IRQ interrupt or an
edge-based PLA interrupt, set the appropriate bit in the IRQCLRE
register.
IRQCONE Register
Name: IRQCONE
Address: 0xFFFF0034
Default Value: 0x00000000
Access: Read/write
Table 138. IRQCONE MMR Bit Descriptions
Bit Value Name Description
[31:12] Reserved. These bits are reserved and should not be written to.
[11:10] 11 PLA1SRC[1:0] PLA IRQ1 triggers on falling edge.
10 PLA IRQ1 triggers on rising edge.
01 PLA IRQ1 triggers on low level.
00 PLA IRQ1 triggers on high level.
[9:8] 11 IRQ3SRC[1:0] External IRQ3 triggers on falling edge.
10 External IRQ3 triggers on rising edge.
01 External IRQ3 triggers on low level.
00 External IRQ3 triggers on high level.