Datasheet

Data Sheet ADuC7124/ADuC7126
Rev. C | Page 9 of 108
SDA (I/O)
t
BUF
MSB LSB ACK MSB
1982–71
SCL (I)
PS
STOP
CONDITION
START
CONDITION
S(R)
REPEATED
START
t
R
t
F
t
F
t
R
t
H
t
L
t
DSU
t
DHD
t
RSU
t
DHD
t
DSU
t
SHD
t
PSU
0
9123-029
Figure 2. I
2
C-Compatible Interface Timing
SPI Timing
Table 4. SPI Master Mode Timing (Phase Mode = 1)
Parameter Description Min Typ Max Unit
t
SL
SCLK low pulse width
1
(SPIDIV + 1) × t
UCLK
ns
t
SH
SCLK high pulse width
1
(SPIDIV + 1) × t
UCLK
ns
t
DAV
Data output valid after SCLK edge 25 ns
t
DSU
Data input setup time before SCLK edge
1
1 × t
UCLK
ns
t
DHD
Data input hold time after SCLK edge
1
2 × t
UCLK
ns
t
DF
Data output fall time 5 12.5 ns
t
DR
Data output rise time 5 12.5 ns
t
SR
SCLK rise time 5 12.5 ns
t
SF
SCLK fall time 5 12.5 ns
1
t
UCLK
= 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider.
0
9123-030
SCLK
(POLARITY = 0)
SCLK
(POLARITY = 1)
MOSI MSB BIT 6 TO BIT 1 LSB
MISO MSB IN BIT 6 TO BIT 1 LSB IN
t
SH
t
SL
t
SR
t
SF
t
DR
t
DF
t
DAV
t
DSU
t
DHD
Figure 3. SPI Master Mode Timing (Phase Mode = 1)