Datasheet

ADuC7124/ADuC7126 Data Sheet
Rev. C | Page 90 of 108
Bit Value Name Description
[7:6] 11 IRQ2SRC[1:0] External IRQ2 triggers on falling edge.
10 External IRQ2 triggers on rising edge.
01 External IRQ2 triggers on low level.
00 External IRQ2 triggers on high level.
[5:4] 11 PLA0SRC[1:0] PLA IRQ0 triggers on falling edge.
10 PLA IRQ0 triggers on rising edge.
01 PLA IRQ0 triggers on low level.
00 PLA IRQ0 triggers on high level.
[3:2] 11 IRQ1SRC[1:0] External IRQ1 triggers on falling edge.
10 External IRQ1 triggers on rising edge.
01 External IRQ1 triggers on low level.
00 External IRQ1 triggers on high level.
[1:0] 11 IRQ0SRC[1:0] External IRQ0 triggers on falling edge.
10 External IRQ0 triggers on rising edge.
01 External IRQ0 triggers on low level.
00 External IRQ0 triggers on high level.
IRQCLRE Register
Name: IRQCLRE
Address: 0xFFFF0038
Default Value: 0x00000000
Access: Write only
Table 139. IRQCLRE MMR Bit Descriptions
Bit Name Description
[31:25] Reserved. These bits are reserved and should not be written to.
24 PLA1CLRI
A 1 must be written to this bit in the PLA IRQ1 interrupt service routine to clear an edge-
triggered PLA IRQ1 interrupt.
23 IRQ3CLRI
A 1 must be written to this bit in the external IRQ3 interrupt service routine to clear an edge-
triggered IRQ3 interrupt.
22 IRQ2CLRI
A 1 must be written to this bit in the external IRQ2 interrupt service routine to clear an edge-
triggered IRQ2 interrupt.
21 PLA0CLRI
A 1 must be written to this bit in the PLA IRQ0 interrupt service routine to clear an edge-
triggered PLA IRQ0 interrupt.
20 IRQ1CLRI
A 1 must be written to this bit in the external IRQ1 interrupt service routine to clear an edge-
triggered IRQ1 interrupt.
[19:18] Reserved. These bits are reserved and should not be written to.
17 IRQ0CLRI
A 1 must be written to this bit in the external IRQ0 interrupt service routine to clear an edge
triggered IRQ0 interrupt.
[16:0] Reserved. These bits are reserved and should not be written to.