Datasheet

Data Sheet ADuC7124/ADuC7126
Rev. C | Page 91 of 108
TIMERS
The ADuC7124/ADuC7126 have four general-purpose
timers/counters.
•
Timer0
•
Timer1
•
Timer2 or wake-up timer
•
Timer3 or watchdog timer
These four timers in their normal mode of operation can be
either free running or periodic.
In free-running mode, the counter decreases from the maxi-
mum value until zero scale is reached and starts again at the
minimum value. It also increases from the minimum value until
full scale is reached and starts again at the maximum value.
In periodic mode, the counter decrements/increments from the
value in the load register (TxLD MMR) until zero/full scale is
reached and starts again at the value stored in the load register.
The timer interval is calculated as follows:
If the timer is set to count down, then
(
)
ClockSource
PrescalerTxLD
Interval
×
=
If the timer is set to count up, then
(
)
ClockSource
PrescalerTxLDFullScale
Interval
×
=
-
The value of a counter can be read at any time by accessing
its value register (TxVAL). Note that, when a timer is being
clocked from a clock other than a core clock, an incorrect
value may be read (due to asynchronous clock system). In this
configuration, TxVAL should always be read twice. If the two
readings are different, it should be read a third time to obtain
the correct value.
Timers are started by writing in the control register of the
corresponding timer (TxCON).
In normal mode, an IRQ is generated each time the value of the
counter reaches zero when counting down. It is also generated
each time the counter value reaches full scale when counting
up. An IRQ can be cleared by writing any value to clear the
register of that particular timer (TxCLRI).
When using an asynchronous clock-to-clock timer, the
interrupt in the timer block can take more time to clear
than the time it takes for the code in the interrupt routine to
execute. Ensure that the interrupt signal is cleared before
leaving the interrupt service routine. This can be done by
checking the IRQSTA MMR.
Hr: Min: Sec: 1/128 Format
Timer 1 and Timer 2 have an Hr: Min: Sec: hundreds format.
To use the timer in Hr: Min: Sec: hundreds format, the
32768 kHz clock and prescaler of 256 should be selected. The
hundreds field does not represent milliseconds, but 1/128 of a
second (256/32768).The bits representing the hour, minute,
and second are not consecutive in the register. This arrange-
ment applies to TxLD and TxVAL when using the Hr: Min: Sec:
hundreds format as set in TxCON[5:4]. See Table 140 for more
details.
Table 140. Hr: Min: Sec: Hundreds Format
Bit Value Description
[31:24] 0 to 23 or 0 to 255 hours
[23:22] 0 reserved
[21:16] 0 to 59 minutes
[15:14] 0 reserved
[13:8] 0 to 59 seconds
7 0 reserved
[6:0] 0 to 127 1/128 of second