Datasheet

ADuC7124/ADuC7126 Data Sheet
Rev. C | Page 96 of 108
Timer3 (Watchdog Time)
Timer3 has two modes of operation: normal mode and
watchdog mode. The watchdog timer is used to recover from
an illegal software state. Once enabled, it requires periodic
servicing to prevent it from forcing a processor reset.
Normal Mode
Timer3 in normal mode is identical to Timer0, except for the
clock source and the count-up functionality. The clock source is
32 kHz from the PLL and can be scaled by a factor of 1, 16, or
256 (see Figure 55).
09123-037
32.768kHz
PRESCALER
÷ 1, 16 OR 256
16-BIT
UP/DOWN
COUNTER
16-BIT
LOAD
TIMER3
VALUE
WATCHDOG
RESET
TIMER3 IRQ
Figure 55. Timer3 Block Diagram
Watchd o g Mo de
Watchdog mode is entered by setting Bit 5 in the T3CON MMR.
Timer3 decreases from the value present in the T3LD register
until 0 is reached. T3LD is used as the timeout. The maximum
timeout can be 512 sec using the prescaler/256 and full scale in
T3LD. Timer3 is clocked by the internal 32 kHz crystal when
operating in the watchdog mode. Note that, to enter watchdog
mode successfully, Bit 5 in the T3CON MMR must be set after
writing to the T3LD MMR.
If the timer reaches 0, a reset or an interrupt occurs, depending
on Bit 1 in the T3CON register. To avoid reset or interrupt, any
value must be written to T3CLRI before the expiration period.
This reloads the counter with T3LD and begins a new timeout
period.
When watchdog mode is entered, T3LD and T3CON are write-
protected. These two registers cannot be modified until a reset
clears the watchdog enable bit, which causes Timer3 to exit
watchdog mode.
The Timer3 interface consists of four MMRs: T3LD, T3VAL,
T3CON, and T3CLRI.
T3LD Register
Name: T3LD
Address: 0xFFFF0360
Default Value: 0x0000
Access: Read/write
T3LD is a 16-bit load register.
T3VAL Register
Name: T3VAL
Address: 0xFFFF0364
Default Value: 0xFFFF
Access: Read only
T3VAL is a 16-bit read-only register that represents the current
state of the counter.
T3CON Register
Name: T3CON
Address: 0xFFFF0368
Default Value: 0x0000
Access: Read/write
T3CON is the configuration MMR described in Table 145.
Table 145. T3CON MMR Bit Descriptions
Bit Value Description
[31:9] Reserved.
8 Count up.
Set by the user for Timer3 to count up.
Cleared by the user for Timer3 to count down
by default.
7 Timer3 enable bit.
Set by the user to enable Timer3.
Cleared by the user to disable Timer3 by
default.
6 Timer3 mode.
Set by the user to operate in periodic mode.
Cleared by the user to operate in free-running
mode (default mode).
5 Watchdog mode enable bit.
Set by the user to enable watchdog mode.
Cleared by the user to disable watchdog
mode by default.
4 Secure clear bit.
Set by the user to use the secure clear option.
Cleared by the user to disable the secure clear
option by default.
[3:2] Prescale.
00 Source clock/1 by default.
01 Source clock/16.
10 Source clock/256.
11 Undefined. Equivalent to 00.
1 Watchdog IRQ option bit.
Set by the user to produce an IRQ instead of a
reset when the watchdog reaches 0.
Cleared by the user to disable the IRQ option.
0 Reserved.