Precision Analog Microcontroller ARM7TDMI MCU with 12-Bit ADC and DDS DAC ADuC7128/ADuC7129 FEATURES In-circuit download, JTAG-based debug Software triggered in-circuit reprogrammability On-chip peripherals 2× UART, 2× I2C and SPI serial I/O Up to 40-pin GPIO port 5× general-purpose timers Wake-up and watchdog timers (WDT) Power supply monitor 16-bit PWM generator Quadrature encoder Programmable logic array (PLA) Power Specified for 3 V operation Active mode 11 mA (@ 5.22 MHz) 45 mA (@ 41.
ADuC7128/ADuC7129 TABLE OF CONTENTS Features .............................................................................................. 1 Execution Time from SRAM and FLASH/EE........................ 43 Functional Block Diagram .............................................................. 1 Reset and Remap ........................................................................ 44 Revision History ...............................................................................
ADuC7128/ADuC7129 GENERAL DESCRIPTION The ADuC7128/ADuC7129 are fully integrated, 1 MSPS, 12-bit data acquisition systems incorporating a high performance, multichannel analog-to-digital converter (ADC), DDS with line driver, 16-/32-bit MCU, and Flash/EE memory on a single chip. The ADC consists of up to 14 single-ended inputs. The ADC can operate in single-ended or differential input modes. The ADC input voltage is 0 to VREF.
ADuC7128/ADuC7129 SPECIFICATIONS AVDD = IOVDD = 3.0 V to 3.6 V, VREF = 2.5 V internal reference, fCORE = 41.78 MHz. All specifications TA = TMAX to TMIN, unless otherwise noted. Table 1. Parameter ADC CHANNEL SPECIFICATIONS ADC Power-Up Time DC Accuracy 1, 2 Resolution Integral Nonlinearity 3 Min Unit Test Conditions/Comments Eight acquisition clocks and fADC/2 μs 12 ±0.7 ±0.7 ±2.0 ±0.5 ±0.
ADuC7128/ADuC7129 Parameter Relative Accuracy Differential Nonlinearity, +VE Differential Nonlinearity, −VE Offset Error Gain Error Voltage Output Settling Time to 0.1% Line Driver Output Min DC Mode 11 dB V rms 1.65 V 1.5 V 13 ±50 20 ±15 1 AGND 15 Input Capacitance pF mV 1 μs 780 −1.3 ±3 mV mV/°C °C 2.79 3.07 ±2.
ADuC7128/ADuC7129 Parameter LOGIC INPUTS3 VINL, Input Low Voltage VINH, Input High Voltage Quadrature Encoder Inputs S1/S2/CLR (Schmitt-Triggered Inputs) VT+ VT− VT+ − VT− LOGIC OUTPUTS 9 VOH, Output High Voltage Min Typ Max Unit 0.8 V V 2.0 1.65 1.2 0.75 V V V IOVDD − 400 mV VOL, Output Low Voltage CRYSTAL INPUTS XCLKI and XCLKO VINL, Input Low Voltage VINH, Input High Voltage XCLKI, Input Capacitance XCLKO, Output Capacitance MCU CLOCK RATE (PLL) 0.4 1.1 1.7 20 20 326.4 41.
ADuC7128/ADuC7129 Line Driver Load 94Ω 100nF 94Ω 100nF 94Ω 100nF 94Ω 118Ω LD2TX LD1TX 57Ω LD2TX 27.5µH 8.9µH 06020-002 100nF LD1TX Figure 2. Line Driver Load Minimum (Top) and Maximum (Bottom) Rev.
ADuC7128/ADuC7129 TIMING SPECIFICATIONS Table 2.
ADuC7128/ADuC7129 Table 3.
ADuC7128/ADuC7129 I2C® Timing Specifications Table 4. I2C Timing in Fast Mode (400 kHz) P P Parameter tL tH tSHD tDSU tDHD tRSU tPSU tBUF tR tF tSUP Slave Min 200 100 300 100 0 100 100 1.3 100 60 Slave Max Master Typ 1360 1140 251,350 740 400 12.51350 400 300 300 50 200 20 Unit ns ns ns ns ns ns ns μs ns ns ns tHCLK depends on the clock divider or CD bits in the PLLCON MMR, tHCLK = tUCLK/2CD.
ADuC7128/ADuC7129 SPI Timing Specifications Table 5. SPI Master Mode Timing (PHASE Mode = 1) Parameter tSL tSH tDAV tDSU tDHD tDF tDR tSR tSF 2 Min Typ (SPIDIV + 1) × tHCLK (SPIDIV + 1) × tHCLK Max 2 × tHCLK + 2 × tUCLK 1 × tUCLK 2 × tUCLK 5 5 5 5 12.5 12.5 12.5 12.5 tHCLK depends on the clock divider or CD bits in the PLLCON MMR, tHCLK = tUCLK/2CD. tUCLK = 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider.
ADuC7128/ADuC7129 Table 6. SPI Master Mode Timing (PHASE Mode = 0) Parameter tSL tSH tDAV tDOSU tDSU tDHD tDF tDR tSR tSF 2 Min Typ (SPIDIV + 1) × tHCLK (SPIDIV + 1) × tHCLK Max 2 × tHCLK + 2 × tUCLK 75 1 × tUCLK 2 × tUCLK 5 5 5 5 12.5 12.5 12.5 12.5 tHCLK depends on the clock divider or CD bits in the PLLCON MMR, tHCLK = tUCLK/2CD. tUCLK = 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider.
ADuC7128/ADuC7129 Table 7. SPI Slave Mode Timing (PHASE Mode = 1) Parameter tCS tSL tSH tDAV tDSU tDHD tDF tDR tSR tSF tSFS 2 Min 2 × tUCLK Typ Max Unit ns ns ns ns ns ns ns ns ns ns ns (SPIDIV + 1) × tHCLK (SPIDIV + 1) × tHCLK 2 × tHCLK + 2 × tUCLK 1 × tUCLK 2 × tUCLK 5 5 5 5 12.5 12.5 12.5 12.5 0 tUCLK = 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider. tHCLK depends on the clock divider or CD bits in the PLLCON MMR, tHCLK = tUCLK/2CD.
ADuC7128/ADuC7129 Table 8. SPI Slave Mode Timing (PHASE Mode = 0) Parameter tCS tSL tSH tDAV tDSU tDHD tDF tDR tSR tSF tDOCS tSFS 2 Min 2 × tUCLK Typ Max (SPIDIV + 1) × tHCLK (SPIDIV + 1) × tHCLK 2 × tHCLK + 2 × tUCLK 1 × tUCLK 2 × tUCLK 5 5 5 5 12.5 12.5 12.5 12.5 25 0 tUCLK = 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider. tHCLK depends on the clock divider or CD bits in the PLLCON MMR, tHCLK = tUCLK/2CD.
ADuC7128/ADuC7129 ABSOLUTE MAXIMUM RATINGS DVDD = IOVDD, AGND = REFGND = DACGND = GNDREF. TA = 25°C, unless otherwise noted. Table 9.
ADuC7128/ADuC7129 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 ADC4 ADC3/CMP1 ADC2/CMP0 ADC1 ADC0 DACV DD AVDD AGND DACGND VREF P4.5 P4.4 P4.3/PWMTRIP P4.2 P1.0/SPM0 P1.1/SPM1 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PIN 1 INDICATOR ADuC7128 TOP VIEW (Not to Scale) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P1.2/SPM2 P1.3/SPM3 P1.4/SPM4 P1.5/SPM5 P4.1/S2 P4.0/S1 IOVDD IOGND P1.6/SPM6 P1.7/SPM7 DGND PVDD XCLKI XCLKO P0.7/SPM8/ECLK/XCLK P2.
ADuC7128/ADuC7129 Pin No. 21 Mnemonic LVDD Type 1 S 22 23 24 25 26 27 DGND P3.0/PWM1 P3.1/PWM2 P3.2/PWM3 P3.3/PWM4 P0.3/ADCBUSY/TRST S I/O I/O I/O I/O I/O 28 29 30 31 RST P3.4/PWM5 P3.5/PWM6 P0.4/IRQ0/CONVST I I/O I/O I/O 32 P0.5/IRQ1/ADCBUSY I/O 33 34 P2.0/SPM9 P0.7/SPM8/ECLK/XCLK I/O I/O 35 36 37 XCLKO XCLKI PVDD O I S 38 39 40 43 44 45 46 47 48 49 50 51 52 53 54 55 DGND P1.7/SPM7 P1.6/SPM6 P4.0/S1 P4.1/S2 P1.5/SPM5 P1.4/SPM4 P1.3/SPM3 P1.2/SPM2 P1.1/SPM1 P1.0/SPM0 P4.2 P4.
P1.1/SPM1 P1.0/SPM0 P4.2/AD10 P4.3/PWMTRIP/AD11 P4.4/AD12 P4.5/AD13 IOGND REFGND VREF DACGND AGND AGND AVDD AVDD DACV DD ADC11 ADC0 ADC1 ADC2/CMP0 ADC3/CMP1 ADuC7128/ADuC7129 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 P1.2/SPM2 59 P1.3/SPM3 3 58 P1.4/SPM4 4 57 P1.5/SPM5 VDACOUT/ADC8 5 56 P4.1/S2/AD9 ADC4 1 ADC5 2 ADC6 ADC7 PIN 1 ADC9 6 55 P4.0/S1/AD8 ADC10 7 54 IOVDD GNDREF 8 53 IOGND ADCNEG 9 ADuC7129 52 P1.
ADuC7128/ADuC7129 Pin No. 17 18 19 Mnemonic P4.6/SPM10/AD14 P4.7/SPM11/AD15 P0.0/BM/CMPOUT/MS0 Type1 I/O I/O I/O 20 21 22 P0.6/T1/MRST TCK TDO/P0.2/BHE O I O 23, 53, 67 24, 54 25 IOGND IOVDD LVDD S S S 26 27 28 29 30 31 32 DGND P3.0/PWM1/AD0 P3.1/PWM2/AD1 P3.2/PWM3/AD2 P3.3/PWM4/AD3 P2.4/MS0 P0.3/ADCBUSY/TRST/A16 S I/O I/O I/O I/O I/O I/O 33 34 35 36 37 38 P2.5/MS1 P2.6/MS2 RST P3.4/PWM5/AD4 P3.5/PWM6/AD5 P0.4/IRQ0/CONVST/MS1 I/O I/O I I/O I/O I/O 39 P0.5/IRQ1/ADCBUSY I/O 40 41 P2.
ADuC7128/ADuC7129 Pin No. 63 64 65 66 68 69 Mnemonic P4.2/AD10 P4.3/PWMTRIP/AD11 P4.4/AD12 P4.5/AD13 REFGND VREF Type1 I/O I/O I/O I/O S I/O 70 71, 72 75 DACGND AGND DACVDD S S S 76 77 78 79 80 ADC11 ADC0 ADC1 ADC2/CMP0 ADC3/CMP1 I I I I I 1 Description General-Purpose Input and Output Port 4.2/External Memory AD10. General-Purpose Input and Output Port 4.3/PWM Safety Cutoff/External Memory AD11. General-Purpose Input and Output Port 4.4/External Memory AD12.
ADuC7128/ADuC7129 TYPICAL PERFORMANCE CHARACTERISTICS 1.0 fS = 774kSPS 0.4 0.2 0.2 (LSB) 0.6 0.4 (LSB) 0.6 0 0 –0.2 –0.2 –0.4 –0.4 –0.6 –0.6 –0.8 –0.8 0 1000 2000 ADC CODES 3000 4000 –1.0 06020-008 –1.0 fS = 774kSPS 0.8 0 Figure 12. Typical INL Error, fS = 774 kSPS 1.0 1.0 0.4 0.2 0.2 (LSB) 0.4 (LSB) 0.6 0 –0.2 –0.4 –0.4 –0.6 –0.6 –0.8 –0.8 2000 ADC CODES 3000 4000 –1.0 06020-009 1000 4000 0 –0.2 0 3000 fS = 1MSPS 0.8 0.6 –1.
ADuC7128/ADuC7129 9000 75 8000 –76 70 –78 SNR 7000 65 60 SNR (dB) FREQUENCY 5000 4000 –82 THD 55 THD (dB) –80 6000 –84 3000 50 2000 1162 BIN 1163 40 1.0 Figure 18. Code Histogram Plot 0 2.0 2.5 EXTERNAL REFERENCE (V) –88 3.0 Figure 21. Typical Dynamic Performance vs. VREF 1500 fS = 774kSPS, SNR = 69.3dB, THD = –80.8dB, PHSN = –83.4dB –20 1.
ADuC7128/ADuC7129 12.05 300 12.00 250 11.95 11.90 200 (µA) (mA) 11.85 11.80 150 11.75 100 11.70 11.65 50 –40 0 25 85 TEMPERATURE (°C) 125 0 06020-020 11.55 Figure 24. Current Consumption vs. Temperature @ CD = 3 –40 25 85 TEMPERATURE (°C) 125 06020-022 11.60 Figure 26. Current Consumption vs. Temperature in Sleep Mode 7.85 37.4 7.80 37.2 7.75 37.0 (mA) 7.65 7.60 36.8 36.6 7.55 7.50 36.4 7.40 –40 0 25 85 TEMPERATURE (°C) 125 Figure 25. Current Consumption vs.
ADuC7128/ADuC7129 TERMINOLOGY ADC SPECIFICATIONS Integral Nonlinearity The maximum deviation of any code from a straight line passing through the endpoints of the ADC transfer function. The endpoints of the transfer function are zero scale, a point ½ LSB below the first code transition and full scale, a point ½ LSB above the last code transition. Differential Nonlinearity The difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC.
ADuC7128/ADuC7129 OVERVIEW OF THE ARM7TDMI CORE The ARM7 core is a 32-bit reduced instruction set computer (RISC). It uses a single 32-bit bus for instruction and data. The length of the data can be 8 bits, 16 bits, or 32 bits. The length of the instruction word is 32 bits. The ARM7TDMI is an ARM7 core with the following four additional features: • • • • • • • • An ARM® instruction is 32-bits long.
ADuC7128/ADuC7129 R0 USABLE IN USER MODE R1 At the end of this time, the ARM7TDMI executes the instruction at Address 0x1C (FIQ interrupt vector address). The maximum total time is 50 processor cycles, which is just under 1.2 μs in a system using a continuous 41.78 MHz processor clock.
ADuC7128/ADuC7129 MEMORY ORGANIZATION The ADuC7128/ADuC7129 incorporate three separate blocks of memory: 8 kB of SRAM and two 64 kB of on-chip Flash/EE memory. There are 126 kB of on-chip Flash/EE memory available to the user, and the remaining 2 kB are reserved for the factoryconfigured boot page. These two blocks are mapped as shown in Figure 29. Note that by default, after a reset, the Flash/EE memory is mirrored at Address 0x00000000.
ADuC7128/ADuC7129 0xFFFFFFFF 0xFFFF0690 0xFFFF0F80 0xFFFF0F18 QEN DAC 0xFFFF0F00 0xFFFF0EA8 0xFFFF0544 0xFFFF0500 0xFFFF04A8 0xFFFF0480 0xFFFF0448 0xFFFF0440 0xFFFF0434 0xFFFF0400 0xFFFF0394 0xFFFF0380 0xFFFF0370 0xFFFF0360 0xFFFF0350 0xFFFF0340 0xFFFF0334 0xFFFF0320 ADC 0xFFFF0E80 0xFFFF0E28 BANDGAP REFERENCE 0xFFFF0E00 0xFFFF0200 0xFFFF0110 0xFFFF0000 FLASH CONTROL INTERFACE 0 GPIO 0xFFFF0D00 0xFFFF0C30 PLL AND OSCILLATOR CONTROL EXTERNAL MEMORY 0xFFFF0C00 0xFFFF0B54 GENERAL PURPOSE TIMER
ADuC7128/ADuC7129 Table 18. ADC Base Address = 0xFFFF0500 Address 0x0500 0x0504 0x0508 0x050C 0x0510 0x0514 Name ADCCON ADCCP ADCCN ADCSTA ADCDAT ADCRST Byte 2 1 1 1 4 1 Access Type R/W R/W R/W R R W Table 22. I2C0 Base Address = 0xFFFF0800 Cycle 2 2 2 2 2 2 Table 19.
ADuC7128/ADuC7129 Table 27. GPIO Base Address = 0xFFFF0D00 Table 25.
ADuC7128/ADuC7129 Table 31. PWM Base Address = 0xFFFF0F80 Table 30. QEN Base Address = 0xFFFF0F00 Address 0x0F00 0x0F04 0x0F08 0x0F0C 0x0F14 0x0F18 Name QENCON QENSTA QENDAT QENVAL QENCLR QENSET Byte 2 1 2 2 1 1 Access Type R/W R R/W R W W Cycle 2 2 2 2 2 2 Address 0x0F80 0x0F84 0x0F88 0x0F8C 0x0F90 0x0F94 0x0F98 0x0F9C 0x0FA0 0x0FA4 0x0FA8 0x0FAC 0x0FB0 0x0FB4 0x0FB8 Rev.
ADuC7128/ADuC7129 ADC CIRCUIT OVERVIEW The ADC consists of a 12-bit successive approximation converter based around two capacitor DACs.
ADuC7128/ADuC7129 SIGN BIT 0 1111 1111 1110 0 1111 1111 1100 Current Consumption The ADC in standby mode, that is, powered up but not converting, typically consumes 640 μA. The internal reference adds 140 μA. During conversion, the extra current is 0.3 μA, multiplied by the sampling frequency (in kHz). 2 × VREF 4096 1LSB = 0 0000 0000 0001 0 0000 0000 0000 Timing 1 1111 1111 1110 Figure 36 gives details of the ADC timing.
ADuC7128/ADuC7129 Table 33. ADCCON MMR Bit Designations Bit 12:10 Value 000 001 010 011 100 101 9:8 00 01 10 11 7 6 5 4:3 00 01 10 11 2:0 000 Description ADC Clock Speed (fADC = FCORE, Conversion = 19 ADC Clocks + Acquisition Time). fADC/1. This divider is provided to obtain 1 MSPS ADC with an external clock <41.78 MHz. fADC/2 (default value). fADC/4. fADC/8. fADC/16. fADC/32. ADC Acquisition Time (Number of ADC Clocks). 2 clocks. 4 clocks. 8 clocks (default value). 16 clocks. Enable Conversion.
ADuC7128/ADuC7129 Table 34. ADCCP1 MMR Bit Designations Table 35.
ADuC7128/ADuC7129 CONVERTER OPERATION Pseudo Differential Mode The ADC incorporates a successive approximation (SAR) architecture involving a charge-sampled input stage. This architecture is described for the three different modes of operation: differential mode, pseudo differential mode, and single-ended mode. In pseudo differential mode, Channel− is linked to the VIN− pin of the ADuC7128/ADuC7129, and SW2 switches between A (Channel−) and B (VREF).
ADuC7128/ADuC7129 AVDD D C1 Table 39. VCM Ranges AVDD 3.3 V R1 C2 D 3.0 V AVDD D Figure 41. Equivalent Analog Input Circuit Conversion Phase: Switches Open, Track Phase: Switches Closed For ac applications, removing high frequency components from the analog input signal is recommended through the use of an RC low-pass filter on the relevant analog input pins.
ADuC7128/ADuC7129 BAND GAP REFERENCE The ADuC7128/ADuC7129 provide an on-chip band gap reference of 2.5 V that can be used for the ADC and for the DAC. This internal reference also appears on the VREF pin. When using the internal reference, a capacitor of 0.47 μF must be connected from the external VREF pin to AGND to ensure stability and fast response during ADC conversions. This reference can also be connected to an external pin (VREF) and used as a reference for other circuits in the system.
ADuC7128/ADuC7129 NONVOLATILE FLASH/EE MEMORY Like EEPROM, Flash memory can be programmed in-system at a byte level, although it must first be erased. The erase is performed in page blocks. As a result, Flash memory is often, and more correctly, referred to as Flash/EE memory. Overall, Flash/EE memory represents a step closer to the ideal memory device that includes nonvolatility, in-circuit programmability, high density, and low cost.
ADuC7128/ADuC7129 FLASH/EE MEMORY SECURITY The 126 kB of Flash/EE memory available to the user can be read and write protected. Bit 31 of the FEE0PRO/FEE0HID MMR protects the 126 kB from being read through JTAG and also in parallel programming mode. The other 31 bits of this register protect writing to the Flash/EE memory; each bit protects four pages, that is, 2 kB. Write protection is activated for all access types. FEE1PRO and FEE1HID similarly protect the second 64 kB block.
ADuC7128/ADuC7129 FEE1DAT Register Name FEE1DAT Address 0xFFFF0E8C FEE0STA Register Default Value 0xXXXX Access R/W FEE1DAT is a 16-bit data register. Address 0xFFFF0E90 Default Value 0x0000 Address 0xFFFF0E00 Access R/W Name FEE1STA Address 0xFFFF0E80 FEE1ADR is a 16-bit address register. FEE0MOD Register FEE1SGN Register Name FEE0MOD Name FEE1SGN Address 0xFFFF0E98 Default Value 0xFFFFFF Access R FEE1SGN is a 24-bit code signature.
ADuC7128/ADuC7129 Table 41. FEExSTA MMR Bit Designations Bit 15:6 5 4 3 2 1 0 Description Reserved. Reserved. Reserved. Flash/EE Interrupt Status Bit. Set automatically when an interrupt occurs, that is, when a command is complete and the Flash/EE interrupt enable bit in the FEExMOD register is set. Cleared when reading FEExSTA register. Flash/EE Controller Busy. Set automatically when the controller is busy. Cleared automatically when the controller is not busy. Command Fail.
ADuC7128/ADuC7129 Table 44. FEE0PRO and FEE0HID MMR Bit Designations Bit 31 30:0 Description Read Protection. Cleared by user to protect Block 0. Set by user to allow reading Block 0. Write Protection for Page 123 to Page 120, for Page 119 to Page 116, and for Page 3 to Page 0. Cleared by user to protect the pages in writing. Set by user to allow writing the pages. Table 45. FEE1PRO and FEE1HID MMR Bit Designations Bit 31 30 31:0 Description Read Protection. Cleared by user to protect Block 1.
ADuC7128/ADuC7129 RESET AND REMAP Remap Operation The ARM exception vectors are all situated at the bottom of the memory array, from Address 0x00000000 to Address 0x00000020, as shown in Figure 45. When a reset occurs on the ADuC7128/ADuC7129, execution starts automatically in factory-programmed internal configuration code. This kernel is hidden and cannot be accessed by user code.
ADuC7128/ADuC7129 OTHER ANALOG PERIPHERALS DAC The ADuC7128/ADuC7129 feature a 10-bit current DAC that can be used to generate user-defined waveforms or sine waves generated by the DDS. The DAC consists of a 10-bit IDAC followed by a current-to-voltage conversion. The current output of the IDAC is passed through a resistor and capacitor network where it is both filtered and converted to a voltage. This voltage is then buffered by an op amp and passed to the line driver.
ADuC7128/ADuC7129 DACEN Register Name DACEN Address 0xFFFF06B8 Default Value 0x00 Access R/W Table 50. DACEN MMR Bit Designations Bit 7:1 0 DACEN and DACDAT require key access. To write to these MMRs, use the sequences shown in Table 52. Description Reserved. Set to 1 by the user to enable DAC mode. Set to 0 by the user to enable DDS mode. Table 52. DACEN and DACDAT Write Sequences DACDAT Register Name DACDAT Address 0xFFFF06B4 Default Value 0x0000 Table 51.
ADuC7128/ADuC7129 DDSFRQ Register Address 0xFFFF0694 Default Value 0x00000000 Access R/W Table 54. DDSFRQ MMR Bit Designations The PSM does not operate correctly when using JTAG debug. It should be disabled in JTAG debug mode. Description Frequency select word (FSW) The DDS frequency is controlled via the DDSFRQ MMR. This MMR contains a 32-bit word (FSW) that controls the frequency according to the following formula: Frequency = FSW × 20.
ADuC7128/ADuC7129 Comparator Interface The comparator interface consists of a 16-bit MMR, CMPCON, described in Table 57. Table 57. CMPCON MMR Bit Designations Bit 15:11 10 Value Name CMPEN 9:8 CMPIN 00 01 10 11 7:6 CMPOC 00 01 10 11 5 CMPOL 4:3 CMPRES 00 01 10 11 2 CMPHYST 1 CMPORI 0 CMPOFI Description Reserved. Comparator Enable Bit. Set by user to enable the comparator. Cleared by user to disable the comparator. Note: A comparator interrupt is generated on the enable of the comparator.
ADuC7128/ADuC7129 Example Source Code OSCILLATOR AND PLL—POWER CONTROL The ADuC7128/ADuC7129 integrate a 32.768 kHz oscillator, a clock divider, and a PLL. The PLL locks onto a multiple (1275) of the internal oscillator to provide a stable 41.78 MHz clock for the system. The core can operate at this frequency, or at binary submultiples of it, to allow power saving. The default core clock is the PLL clock divided by 8 (CD = 3) or 5.2 MHz.
ADuC7128/ADuC7129 Table 58. Operating Modes Mode Active Pause Nap Sleep Stop Core On Peripherals On On PLL On On On XTAL/T2/T3 On On On On XIRQ On On On On On Start-Up/Power-On Time 130 ms at CD = 0 24 ns at CD = 0; 3.06 μs at CD = 7 24 ns at CD = 0; 3.06 μs at CD = 7 1.58 ms 1.7 ms Table 59. Typical Current Consumption at 25°C PC[2:0] 000 001 010 011 100 Mode Active Pause Nap Sleep Stop CD = 0 33.1 22.7 3.8 0.4 0.4 CD = 1 21.2 13.3 3.8 0.4 0.4 CD = 2 13.8 8.5 3.8 0.4 0.
ADuC7128/ADuC7129 DIGITAL PERIPHERALS PWM GENERAL OVERVIEW HIGH SIDE (PWM1) The ADuC7128/ADuC7129 integrate a six channel PWM interface. The PWM outputs can be configured to drive an H-bridge or can be used as standard PWM outputs. On power up, the PWM outputs default to H-bridge mode. This ensures that the motor is turned off by default. In standard PWM mode, the outputs are arranged as three pairs of PWM pins.
ADuC7128/ADuC7129 Bit 6 Name PWMCP0 5 POINV 4 HOFF 3 LCOMP 2 DIR 1 HMODE 0 PWMEN Description 2. 4. 8. 16. 32. 64. 128. 256. Set to 1 by the user to invert all PWM outputs. Cleared by user to use PWM outputs as normal. High Side Off. Set to 1 by the user to force PWM1 and PWM3 outputs high. This also forces PWM2 and PWM4 low. Cleared by user to use the PWM outputs as normal. Load Compare Registers.
ADuC7128/ADuC7129 Table 67. PWMCON2 MMR Bit Designations Quadrature Encoder Bit 7 A quadrature encoder is used to determine both the speed and direction of a rotating shaft. In its most common form, there are two digital outputs, S1 and S2. As the shaft rotates, both S1 and S2 toggle; however, they are 90° out of phase. The leading output determines the direction of rotation. The time between each transition indicates the speed of rotation.
ADuC7128/ADuC7129 Table 68. QENCON MMR Bit Designations Bit 15:11 10 Name RSVD FILTEN 9 8 RSVD S2INV 7 S1INV 6 DIRCON 5 S1IRQEN 4 3 RSVD UIRQEN 2 OIREQEN 1 0 RSVD ENQEN Description Reserved. Set to 1 by the user to enable filtering on the S1 pin. Cleared by user to disable filtering on the S1 pin. Reserved. This bit should be set to 0 by the user. Set to 1 by the user to invert the S2 input. Cleared by user to use the S2 input as normal.
ADuC7128/ADuC7129 QENCLR Register Name QENCLR Address 0xFFFF0F14 GENERAL-PURPOSE I/O Default Value 0x00000000 Access R/W Writing any value to the QENCLR register clears the QENVAL register to 0x0000. The bits in this register are undefined. QENSET Register Name QENSET Address 0xFFFF0F18 Default Value 0x00000000 Access R/W Writing any value to the QENSET register loads the QENVAL register with the value in QENDAT. The bits in this register are undefined.
ADuC7128/ADuC7129 Table 70. GPIO Pin Function Designations Port 0 1 2 3 4 1 2 Pin P0.0 P0.11 P0.21 P0.3 P0.4 P0.5 P0.6 P0.7 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P2.0 P2.11 P2.21 P2.31 P2.41 P2.51 P2.61 P2.71 P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.61 P3.71 P4.0 P4.1 P4.2 P4.3 00 GPIO GPIO GPIO GPIO GPIO/IRQ0 GPIO/IRQ1 GPIO/T1 GPIO GPIO/T1 GPIO GPIO GPIO GPIO/IRQ2 GPIO/IRQ3 GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO GPIO P4.4 P4.5 P4.6 P4.
ADuC7128/ADuC7129 GPxDAT Register Name GP0DAT GP1DAT GP2DAT GP3DAT GP4DAT Address 0xFFFF0D20 0xFFFF0D30 0xFFFF0D40 0xFFFF0D50 0xFFFF0D60 SERIAL PORT MUX Default Value 0x000000XX 0x000000XX 0x000000XX 0x000000XX 0x000000XX Access R/W R/W R/W R/W R/W GPxDAT is a Port x configuration and data register. It configures the direction of the GPIO pins of Port x, sets the output value for the pins configured as output, and receives and stores the input value of the pins configured as input. Table 73.
ADuC7128/ADuC7129 Calculation of the baud rate using fractional divider is as follows: Table 77. UART Signal Descriptions Pin SPM0 (Mode 1) SPM1 (Mode 1) SPM2 (Mode 1) SPM3 (Mode 1) SPM4 (Mode 1) SPM5 (Mode 1) SPM6 (Mode 1) SPM7 (Mode 1) SPM8 (Mode 2) SPM9 (Mode 2) Signal SIN0 SOUT0 RTS0 CTS0 RI0 DCD0 DSR0 DTR0 SIN0 SOUT0 Description Serial Receive Data. Serial Transmit Data. Request to Send. Clear to Send. Ring Indicator. Data Carrier Detect. Data Set Ready. Data Terminal Ready. Serial Receive Data.
ADuC7128/ADuC7129 Table 80. COMxCON0 MMR Bit Designations Bit 7 Value Name DLAB 6 BRK 5 SP 4 EPS 3 PEN 2 STOP 1:0 WLS 00 01 10 11 Description Divisor Latch Access. Set by user to enable access to COMxDIV0 and COMxDIV1 registers. Cleared by user to disable access to COMxDIV0 and COMxDIV1 and enable access to COMxRX and COMxTX. Set Break. Set by user to force SOUT to 0. Cleared to operate in normal mode. Stick Parity. Set by user to force parity to defined values.
ADuC7128/ADuC7129 Table 82. COMxIEN0 MMR Bit Designations Bit 7:4 3 Name RSVD EDSSI 2 ELSI 1 ETBEI 0 ERBFI Description Reserved. Modem Status Interrupt Enable Bit. Set by user to enable generation of an interrupt if any of COMxSTA1[3:0] are set. Cleared by user. RX Status Interrupt Enable Bit. Set by user to enable generation of an interrupt if any of COMxSTA0[3:1] are set. Cleared by user. Enable Transmit Buffer Empty Interrupt.
ADuC7128/ADuC7129 Table 85. COMxSTA1 MMR Bit Designations Bit 7 6 5 4 3 Name DCD RI DSR CTS DDCD 2 TERI 1 DDSR 0 DCTS Description Data Carrier Detect. Ring Indicator. Data Set Ready. Clear to Send. Delta Data Carrier Detect. Set automatically if DCD changed state since COMxSTA1 last read. Cleared automatically by reading COMxSTA1. Trailing Edge Ring Indicator. Set if NRI changed from 0 to 1 since COMxSTA1 last read. Cleared automatically by reading COMxSTA1. Delta Data Set Ready.
ADuC702x Series Preliminary Technical Data Table 87. COMxIEN1 MMR Bit Designations Bit 7 Name ENAM 6 E9BT 5 E9BR 4 3 ENI E9BD 2 ETD 1 0 NABP NAB Description Network Address Mode Enable Bit. Set by user to enable network address mode. Cleared by user to disable network address mode. 9-Bit Transmit Enable Bit. Set by user to enable 9-bit transmit. ENAM must be set. Cleared by user to disable 9-bit transmit. 9-Bit Receive Enable Bit. Set by user to enable 9-bit receive. ENAM must be set.
ADuC7128/ADuC7129 SERIAL PERIPHERAL INTERFACE The ADuC7128/ADuC7129 integrate a complete hardware serial peripheral interface (SPI) on-chip. SPI is an industrystandard synchronous serial interface that allows eight bits of data to be synchronously transmitted and simultaneously received, that is, full duplex up to a maximum bit rate of 3.4 Mbs. The SPI interface is operational only with core clock divider bits POWCON[2:0] = 0, 1, or 2.
ADuC7128/ADuC7129 SPIRX Register Name SPIRX Address 0xFFFF0A04 SPIDIV Register Default Value 0x00 Access R SPIRX is an 8-bit read-only receive register. Address 0xFFFF0A08 Address 0xFFFF0A0C Default Value 0x1B Access R/W SPIDIV is an 8-bit serial clock divider register. SPITX Register Name SPITX Name SPIDIV SPICON Register Default Value 0x00 SPITX is an 8-bit write-only transmit register.
ADuC7128/ADuC7129 I2C-COMPATIBLE INTERFACES Slave Addresses The ADuC7128/ADuC7129 support two fully licensed I2C interfaces. The I2C interfaces are both implemented as full hardware master and slave interfaces. Because the two I2C interfaces are identical, only I2C0 is described in detail. Note that the two masters and slaves have individual interrupts. Register I2C0ID0, Register I2C0ID1, Register I2C0ID2, and Register I2C0ID3 contain the device IDs.
ADuC7128/ADuC7129 I2CxSSTA Register Name I2C0SSTA I2C1SSTA Address 0xFFFF0804 0xFFFF0904 Default Value 0x01 0x01 Access R R I2CxSSTA is a status register for the slave channel. Table 93. I2CxSSTA MMR Bit Designations Bit 31:15 14 Value 13 12:11 00 01 10 11 10 9:8 00 01 10 11 7 6 5 4 3 2 1 0 Description Reserved. These bits should be written as 0. START Decode Bit. Set by hardware if the device receives a valid start and matching address.
I2CxADR Register I2CxSRX Register Name I2C0SRX I2C1SRX Address 0xFFFF0808 0xFFFF0908 Default Value 0x00 0x00 Access R R I2CxSRX is a receive register for the slave channel.
ADuC7128/ADuC7129 Bit 7 6 5 4 3 2 1 0 Description Master Serial Clock Enable Bit. Set by user to enable generation of the serial clock in master mode. Cleared by user to disable serial clock in master mode. Loop-Back Enable Bit. Set by user to internally connect the transition to the reception to test user software. Cleared by user to operate in normal mode. Start Back-Off Disable Bit. Set by user in multimaster mode. If losing arbitration, the master immediately tries to retransmit.
ADuC7128/ADuC7129 I2CxFIF Register Name I2C0FIF I2C1FIF Address 0xFFFF084C 0xFFFF094C Default Value 0x0000 0x0000 Access R R I2CxFIF is a FIFO status register. Table 95. I2C0FIF MMR Bit Designations Bit 15:10 9 Value 8 7:6 00 01 10 11 5:4 00 01 10 11 3:2 00 01 10 11 1:0 00 01 10 11 Description Reserved. Master Transmit FIFO Flush. Set by user to flush the master Tx FIFO. Cleared automatically once the master Tx FIFO is flushed. This bit also flushes the slave receive FIFO. Slave Transmit FIFO Flush.
ADuC7128/ADuC7129 Table 96. Element Input/Output Table 97. PLA MMRs PLA Block 0 Element Input Output 0 P1.0 P1.7 1 P1.1 P0.4 2 P1.2 P0.5 3 P1.3 P0.6 4 P1.4 P0.7 5 P1.5 P2.0 6 P1.6 P2.1 7 P0.0 P2.2 Name PLAELMx PLA Block 1 Element Input Output 8 P3.0 P4.0 9 P3.1 P4.1 10 P3.2 P4.2 11 P3.3 P4.3 12 P3.4 P4.4 13 P3.5 P4.5 14 P3.6 P4.6 15 P3.7 P4.7 PLACLK PLAIRQ PLAADC PLADIN PLAOUT PLA MMRs Interface The PLA peripheral interface consists on 21 MMRs, as shown in Table 97.
Table 99. PLACLK MMR Bit Designations Table 101. PLAADC MMR Bit Designations Bit 7 6:4 Bit 31:5 4 Value 000 001 010 011 100 101 110 Other 3 2:0 000 001 010 011 100 101 110 Other Description Reserved. Block 1 Clock Source Selection. GPIO Clock on P0.5. GPIO Clock on P0.0. GPIO Clock on P0.7. HCLK. OCLK. Timer1 Overflow. Timer4 Overflow. Reserved. Reserved. Block 0 Clock Source Selection. GPIO Clock on P0.5. GPIO Clock on P0.0. GPIO Clock on P0.7. HCLK. OCLK. Timer1 Overflow. Timer4 Overflow. Reserved.
ADuC7128/ADuC7129 PROCESSOR REFERENCE PERIPHERALS INTERRUPT SYSTEM IRQ There are 30 interrupt sources on the ADuC7128/ADuC7129 controlled by the interrupt controller. Most interrupts are generated from the on-chip peripherals, such as ADC and UART. Two additional interrupt sources are generated from external interrupt request pins, XIRQ0 and XIRQ1. The ARM7TDMI CPU core only recognizes interrupts as one of two types: a normal interrupt request (IRQ) or a fast interrupt request (FIQ).
ADuC7128/ADuC7129 Programmed Interrupts In normal mode, an IRQ is generated each time the value of the counter reaches zero, if counting down; or full scale, if counting up. An IRQ can be cleared by writing any value to clear the register of the particular timer (TxICLR). As the programmed interrupts are nonmaskable, they are controlled by the SWICFG register that writes into both the IRQSTA and IRQSIG registers and/or FIQSTA and FIQSIG registers at the same time.
ADuC7128/ADuC7129 The Timer0 interface consists of six MMRs, shown in Table 108. Timer0 Control Register Table 108. Timer0 Interface MMRs Name T0CON Name T0LD T0CAP T0VAL0/ T0VAL1 T0ICLR T0CON Description A 16-bit register that holds the 16-bit value loaded into the counter. Available only in 16-bit mode. A 16-bit register that holds the 16-bit value captured by an enabled IRQ event. Available only in 16-bit mode. TOVAL0 is a 16 bit register that holds the 16 least significant bits (LSBs).
ADuC7128/ADuC7129 Timer1 reloads the value from T1LD either when Timer1 overflows or immediately after T1ICLR is written. TIMER1—GENERAL-PURPOSE TIMER 32-BIT LOAD 32.768kHz OSCILLATOR Timer1 Load Register CORE CLOCK FREQUENCY PRESCALER 1, 16, 256, OR 32768 GPIO 32-BIT UP/DOWN COUNTER Name Address Default Value Access T1LD 0xFFFF0320 0x00000 R/W T1LD is a 32-bit register that holds the 32-bit value that is loaded into the counter.
ADuC7128/ADuC7129 Table 111. T1CON MMR Bit Designations Bit 31:18 17 Value 16:12 11:9 000 001 010 011 8 7 6 5:4 00 01 10 11 3:0 0000 0100 1000 1111 Description Reserved. Should be set to 0 by the user. Event Select Bit. Set by user to enable time capture of an event. Cleared by user to disable time capture of an event. Event Select Range, 0 to 31. The events are as described in the introduction to the timers. Clock Select. Core Clock (Default). 32.768 kHz Oscillator. P1.0. P0.6. Count Up.
ADuC7128/ADuC7129 Timer2 Load Register TIMER2—WAKE-UP TIMER Name T2LD 32-BIT LOAD EXTERNAL 32kHz OSCILLATOR INTERNAL 32kHz OSCILLATOR PRESCALER 1, 16, 256, OR 32768 32-BIT UP/DOWN COUNTER Address 0xFFFF0340 Default Value 0x00000 Access R/W T2LD is a 32-bit register that holds the 32 bit value that is loaded into the counter. TIMER2IRQ TIMER2 VALUE 06020-052 CORE CLOCK Figure 57.
ADuC7128/ADuC7129 Table 113. T2CON MMR Bit Designations Bit 31:11 10:9 Value 00 01 10 11 8 7 6 5:4 00 01 10 11 3:0 0000 0100 1000 1111 Description Reserved. Clock Source Select. Core Clock (Default). Internal 32.768 kHz Oscillator. External 32.768 kHz Watch Crystal. External 32.768 kHz Watch Crystal. Count Up. Set by user for Timer2 to count up. Cleared by user for Timer2 to count down (default). Timer2 Enable Bit. Set by user to enable Timer2. Cleared by user to disable Timer2 (default). Timer2 Mode.
ADuC7128/ADuC7129 Timer3 is automatically halted during JTAG debug access and only recommences counting once JTAG has relinquished control of the ARM7 core. By default, Timer3 continues to count during power-down. This can be disabled by setting Bit 0 in T3CON. It is recommended that the default value is used, that is, the watchdog timer continues to count during power-down.
ADuC7128/ADuC7129 Table 115. T3CON MMR Bit Designations Bit 16:9 8 Value 7 6 5 4 3:2 00 01 10 11 1 0 Description These bits are reserved and should be written as 0s by user code. Count Up/Down Enable. Set by user code to configure Timer3 to count up. Cleared by user code to configure Timer3 to count down. Timer3 Enable. Set by user code to enable Timer3. Cleared by user code to disable Timer3. Timer3 Operating Mode. Set by user code to configure Timer3 to operate in periodic mode.
ADuC7128/ADuC7129 Note that if the part is in a low power mode and Timer4 is clocked from the GPIO or oscillator source, Timer4 continues to operate. TIMER4—GENERAL-PURPOSE TIMER 32-BIT LOAD 32.768kHz OSCILLATOR CORE CLOCK FREQUENCY PRESCALER 1, 16, 256, OR 32768 GPIO 32-BIT UP/DOWN COUNTER Timer4 reloads the value from T4LD either when Timer 4 overflows, or immediately when T4ICLR is written. TIMER4IRQ Timer4 Load Register GPIO Name T4LD IRQ[31:0] 06020-055 TIMER1 VALUE CAPTURE Figure 60.
ADuC7128/ADuC7129 Table 117. T4CON MMR Bit Designations Bit 31:18 17 Value 16:12 11:9 000 001 010 011 8 7 6 5:4 00 01 10 11 3:0 0000 0100 1000 1111 Description Reserved. Set by user to 0. Event Select Bit. Set by user to enable time capture of an event. Cleared by user to disable time capture of an event. Event Select Range, 0 to 31. The events are as described in the Timers section. Clock Select. Core Clock (Default). 32.768 kHz Oscillator. P4.6. P4.7. Count Up. Set by user for Timer4 to count up.
ADuC7128/ADuC7129 EXTERNAL MEMORY INTERFACING The ADuC7129 is the only model in the series that features an external memory interface. The external memory interface requires a larger number of pins. This is why it is only available on larger pin count packages. The XMCFG MMR must be set to 1 to use the external port. A16 AD15:0 LATCH The memory interface can address up to four 128 kB regions of asynchronous memory (SRAM and/or EEPROM). CS WS WE RS OE RAM 128k × 8-BIT D0 TO D7 A16 A0:15 Table 118.
ADuC7128/ADuC7129 The XMxPAR are registers that define the protocol used for accessing the external memory for each memory region. Table 121. XMxPAR MMR Bit Designations Bit 15 Description Enable Byte Write Strobe. This bit is only used for two, 8-bit memory sharing the same memory region. Set by user to gate the AD0 output with the WS output. This allows byte write capability without using BHE and BLE signals. Cleared by user to use BHE and BLE signals.
ADuC7128/ADuC7129 HCLK AD16:0 ADDRESS DATA EXTRA ADDRESS HOLD TIME (BIT 10) MSx AE BUS TURN OUT CYCLE (BIT 9) BUS TURN OUT CYCLE (BIT 9) 06020-070 RS Figure 63. External Memory Read Cycle with Address Hold and Bus Turn Cycles HCLK AD16:0 ADDRESS DATA EXTRA ADDRESS HOLD TIME (BIT 10) MSx AE WRITE HOLD ADDRESS AND DATA CYCLES (BIT 8) WRITE HOLD ADDRESS AND DATA CYCLES (BIT 8) Figure 64. External Memory Write Cycle with Address Hold and Write Hold Cycles Rev.
ADuC7128/ADuC7129 HCLK AD16:0 ADDRESS DATA MSx AE 1 ADDRESS WAIT STATE (BIT 14 TO BIT 12) 1 WRITE STROBE WAIT STATE (BIT 7 TO BIT 4) Figure 65. External Memory Write Cycle with Wait States Rev.
ADuC7128/ADuC7129 HARDWARE DESIGN CONSIDERATIONS POWER SUPPLIES The ADuC7128/ADuC7129 operational power supply voltage range is 3.0 V to 3.6 V. Separate analog and digital power supply pins (AVDD and IOVDD, respectively) allow AVDD to be kept relatively free of noisy digital signals often present on the system IOVDD line. In this mode, the part can also operate with split supplies, that is, using different voltage supply levels for each supply.
ADuC7128/ADuC7129 In these cases, tie the AGND pins and IOGND pins of the ADuC7128/ADuC7129 to the analog ground plane, as shown in Figure 69b. In systems with only one ground plane, ensure that the digital and analog components are physically separated onto separate halves of the board such that digital return currents do not flow near analog circuitry and vice versa. The ADuC7128/ ADuC7129 can then be placed between the digital and analog sections, as illustrated in Figure 69c. a. b.
ADuC7128/ADuC7129 3.3V POWER-ON RESET OPERATION IOVDD 2.6V 2.4V TYP 2.4V TYP LVDD 64ms TYP POR 0.12ms TYP 06020-062 An internal power-on reset (POR) is implemented on the ADuC7128/ADuC7129. For LVDD below 2.45 V, the internal POR holds the ADuC7128/ADuC7129 in reset. As LVDD rises above 2.45 V, an internal timer times out for typically 64 ms before the part is released from reset. The user must ensure that the power supply, IOVDD, has reached a stable 3.0 V minimum level by this time.
ADuC7128/ADuC7129 DEVELOPMENT TOOLS An entry level, low cost development system is available for the ADuC7128/ADuC7129. This system consists of the following PC-based (Windows® compatible) hardware and software development tools. IN-CIRCUIT SERIAL DOWNLOADER The serial downloader is a Windows application that allows the user to serially download an assembled program to the on-chip program Flash/EE memory via the serial port on a standard PC.
ADuC7128/ADuC7129 OUTLINE DIMENSIONS 9.00 BSC SQ 0.60 MAX 64 49 48 PIN 1 INDICATOR 8.75 BSC SQ *4.85 EXPOSED PAD 4.70 SQ 4.55 (BOTTOM VIEW) 0.50 0.40 0.30 33 32 16 17 7.50 REF 0.80 MAX 0.65 TYP 12° MAX THE EXPOSE PAD IS NOT CONNECTED INTERNALLY. FOR INCREASED RELIABILITY OF THE SOLDER JOINTS AND MAXIMUM THERMAL CAPABILITY IT IS RECOMMENDED THAT THE PAD BE SOLDERED TO THE GROUND PLANE. 0.05 MAX 0.02 NOM SEATING PLANE 0.50 BSC PIN 1 INDICATOR 1 0.
ADuC7128/ADuC7129 0.75 0.60 0.45 14.20 14.00 SQ 13.80 1.60 MAX 80 61 60 1 PIN 1 12.20 12.00 SQ 11.80 TOP VIEW (PINS DOWN) 0.15 0.05 SEATING PLANE 0.20 0.09 7° 3.5° 0° 0.08 COPLANARITY VIEW A 20 41 21 VIEW A 0.50 BSC LEAD PITCH ROTATED 90° CCW 40 0.27 0.22 0.17 COMPLIANT TO JEDEC STANDARDS MS-026-BDD 051706-A 1.45 1.40 1.35 Figure 75.
