a MicroConverter ®, Multichannel 12-Bit ADC with Embedded Flash MCU ADuC812 FEATURES Analog I/O 8-Channel, High Accuracy 12-Bit ADC On-Chip, 100 ppm/ C Voltage Reference High Speed 200 kSPS DMA Controller for High Speed ADC-to-RAM Capture 2 12-Bit Voltage Output DACs On-Chip Temperature Sensor Function Memory 8K Bytes On-Chip Flash/EE Program Memory 640 Bytes On-Chip Flash/EE Data Memory 256 Bytes On-Chip Data RAM 16M Bytes External Data Address Space 64K Bytes External Program Address Space 8051 Compatib
ADuC812 TABLE OF CONTENTS FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 APPLICATONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . 6 PIN CONFIGURATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1, 2 (AV ADuC812 = DV = 3.0 V or 5.0 V 10%, REF /REF = 2.5 V Internal Reference, MCLKIN = 11.0592 MHz, SPECIFICATIONS f = 200 kHz, DAC V Load to AGND; R = 2 k , C = 100 pF. All specifications T = T to T , unless otherwise noted.
ADuC812 SPECIFICATIONS1, 2 (continued) Parameter ADuC812BS VDD = 5 V VDD = 3 V Unit Test Conditions/Comments DAC AC CHARACTERISTICS Voltage Output Settling Time 15 15 μs typ 10 10 nV sec typ Full-Scale Settling Time to within 1/2 LSB of Final Value 1 LSB Change at Major Carry 2.3/VDD 150 2.5 ± 2.5% 2.5 100 2.3/VDD 150 2.5 ± 2.5% 2.
ADuC812 Parameter ADuC812BS VDD = 5 V VDD = 3 V Unit Test Conditions/Comments DIGITAL OUTPUTS Output High Voltage (VOH) 2.4 2.4 V min 4.0 2.6 V typ VDD = 4.5 V to 5.5 V ISOURCE = 80 μA VDD = 2.7 V to 3.3 V ISOURCE = 20 μA 0.4 0.2 0.4 0.2 ±10 ±1 10 0.4 0.2 0.4 0.2 ±10 ±1 10 V max V typ V max V typ μA max μA typ pF typ ISINK = 1.6 mA ISINK = 1.
ADuC812 Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . 150°C θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . . 90°C/W Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . 215°C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C ABSOLUTE MAXIMUM RATINGS* (TA = 25°C, unless otherwise noted.) AVDD to DVDD . . . . . . . . . . . . . .
ADuC812 PIN FUNCTION DESCRIPTIONS Mnemonic Type Function DVDD AVDD CREF VREF P P I I/O AGND P1.0–P1.7 G I ADC0–ADC7 T2 I I T2EX I SS SDATA SCLOCK MOSI MISO DAC0 DAC1 RESET I I/O I/O I/O I/O O O I P3.0–P3.7 I/O RxD TxD INT0 I/O O I INT1 I T0 T1 CONVST I I I WR RD XTAL2 XTAL1 DGND P2.0–P2.7 (A8–A15) (A16–A23) O O O I G I/O REV. F Digital Positive Supply Voltage, 3 V or 5 V Nominal. Analog Positive Supply Voltage, 3 V or 5 V Nominal. Decoupling Input for On-Chip Reference. Connect 0.
ADuC812 PIN FUNCTION DESCRIPTIONS (continued) Mnemonic Type Function PSEN O ALE O EA I P0.7–P0.0 (A0–A7) I/O EP Program Store Enable, Logic Output. This output is a control signal that enables the external program memory to the bus during external fetch operations. It is active every six oscillator periods except during external data memory accesses. This pin remains high during internal program execution.
ADuC812 ARCHITECTURE, MAIN FEATURES 7FH The ADuC812 is a highly integrated, true 12-bit data acquisition system. At its core, the ADuC812 incorporates a high performance 8-bit (8052 compatible) MCU with on-chip reprogrammable nonvolatile Flash program memory controlling a multichannel (eight input channels) 12-bit ADC. 2FH BANKS SELECTED VIA BITS IN PSW The chip incorporates all secondary functions to fully support the programmable data acquisition core.
ADuC812 OVERVIEW OF MCU-RELATED SFRs Accumulator SFR Power Control SFR ACC is the Accumulator register and is used for math operations including addition, subtraction, integer multiplication and division, and Boolean bit manipulations. The mnemonics for accumulator-specific instructions refer to the Accumulator as A. B SFR The Power Control (PCON) register contains bits for power saving options and general-purpose status flags as shown in Table II.
ADuC812 SPECIAL FUNCTION REGISTERS All registers except the program counter and the four general-purpose register banks reside in the special function register (SFR) area. The SFR registers include control, configuration, and data registers that provide an interface between the CPU and other on-chip peripherals. Figure 4 shows a full SFR memory map and SFR contents on reset. Unoccupied SFR locations are shown dark shaded (NOT USED). Unoccupied locations in the SFR address space are not implemented, i.e.
ADuC812 ADC CIRCUIT INFORMATION General Overview ADC Transfer Function The ADC conversion block incorporates a fast, 8-channel, 12-bit, single-supply ADC. This block provides the user with multichannel mux, track-and-hold, on-chip reference, calibration features, and ADC. All components in this block are easily configured via a 3-register SFR interface. The ADC consists of a conventional successive-approximation converter based around a capacitor DAC.
ADuC812 ADCCON1—(ADC Control SFR #1) The ADCCON1 register controls conversion and acquisition times, hardware conversion modes and power-down modes as detailed below. SFR Address EFH SFR Power-On Default Value 20H MD1 MD0 CK1 CK0 AQ1 AQ0 T2C EXC Table III. ADCCON1 SFR Bit Designations Bit Name Description ADCCON1.7 MD1 ADCCON1.
ADuC812 ADCCON2—(ADC Control SFR #2) The ADCCON2 register controls ADC channel selection and conversion modes as detailed below. SFR Address SFR Power-On Default Value ADCI DMA D8H 00H CCONV SCONV CS3 CS2 CS1 CS0 Table IV. ADCCON2 SFR Bit Designations Location Name ADCCON2.7 ADCI ADCCON2.6 DMA ADCCON2.5 CCONV ADCCON2.4 SCONV ADCCON2.3 ADCCON2.2 ADCCON2.1 ADCCON2.
ADuC812 Driving the ADC The ADC incorporates a successive approximation (SAR) architecture involving a charge-sampled input stage. Figure 7 shows the equivalent circuit of the analog input section. Each ADC conversion is divided into two distinct phases as defined by the position of the switches in Figure 7. During the sampling phase (with SW1 and SW2 in the “track” position), a charge proportional to the voltage on the analog input is developed across the input sampling capacitor.
ADuC812 However, be sure to include the Schottky diodes shown in Figure 8 (or at least the lower of the two diodes) to protect the analog input from undervoltage conditions. To summarize this section, use the circuit of Figure 8 to drive the analog input pins of the ADuC812. ADuC812 VDD 51 EXTERNAL VOLTAGE REFERENCE VREF Voltage Reference Connections The on-chip 2.5 V band gap voltage reference can be used as the reference source for the ADC and DACs.
ADuC812 without any interaction from the ADuC812 core. This mode allows the ADuC812 to capture a contiguous sample stream at full ADC update rates (200 kHz). 00000AH DMA Mode Configuration Example To set the ADuC812 into DMA mode, a number of steps must be followed. 1. The ADC must be powered down by setting MD1 and MD0 to 0 in ADCCON1. 2. The DMA Address pointer must be set to the start address of where the ADC results are to be written.
ADuC812 and the gain calibration coefficient is divided into ADCGAINH (six bits) and ADCGAINL (eight bits). The offset calibration coefficient compensates for dc offset errors in both the ADC and the input signal. EPROM TECHNOLOGY Increasing the offset coefficient compensates for positive offset, and effectively pushes the ADC transfer function DOWN. Decreasing the offset coefficient compensates for negative offset, and effectively pushes the ADC transfer function UP.
ADuC812 Using the Flash/EE Program Memory This 8K byte Flash/EE program memory array is mapped into the lower 8K bytes of the 64K bytes program space addressable by the ADuC812 and will be used to hold user code in typical applications. Using the Flash/EE Data Memory The user Flash/EE data memory array consists of 640 bytes that are configured into 160 (Page 00H to Page 9FH) 4-byte pages, as shown in Figure 16.
ADuC812 ECON—Flash/EE Memory Control SFR Using the Flash/EE Memory Interface This SFR acts as a command interpreter and may be written with one of five command modes to enable various read, program, and erase cycles as detailed in Table VII. As with all Flash/EE memory architectures, the array can be programmed in system at a byte level, although it must be erased first, the erasure being performed in page blocks (4-byte pages in this case). Table VII.
ADuC812 USER INTERFACE TO OTHER ON-CHIP ADuC812 PERIPHERALS The following section gives a brief overview of the various peripherals also available on-chip. A summary of the SFRs used to control and configure these peripherals is also given. DAC The ADuC812 incorporates two 12-bit voltage output DACs on-chip. Each has a rail-to-rail voltage output buffer capable DACCON DAC Control Register SFR Address Power-On Default Value Bit Addressable FDH 04H No MODE RNG1 RNG0 of driving 10 kΩ/100 pF.
ADuC812 Using the DAC VDD The on-chip DAC architecture consists of a resistor string DAC followed by an output buffer amplifier, the functional equivalent of which is illustrated in Figure 18. Details of the actual DAC architecture can be found in U.S. Patent Number 5969657 (www.uspto.gov). Features of this architecture include inherent guaranteed monotonicity and excellent differential linearity.
ADuC812 the DAC outputs will remain at ground potential whenever the DAC is disabled. However, each DAC output will still spike briefly when power is first applied to the chip, and again when each DAC is first enabled in software. Typical scope shots of these spikes are given in Figure 23 and Figure 24, respectively. OUTPUT VOLTAGE – V 3 2 200 s/DIV AVDD – 2V/DIV 1 0 0 5 10 SOURCE/SINK CURRENT – mA 15 Figure 21.
ADuC812 user program fails to set the watchdog timer refresh bits (WDR1, WDR2) within a predetermined amount of time (see PRE2–0 bits in WDCON). The watchdog timer itself is a 16-bit counter. The watchdog timeout interval can be adjusted via the PRE2–0 bits in WDCON. Full Control and Status of the watchdog timer function can be controlled via the watchdog timer control SFR (WDCON).
ADuC812 PSMCON Power Supply Monitor Control Register SFR Address Power-On Default Value Bit Addressable DFH DCH No — CMP PSMI TP2 TP1 TP0 PSF PSMEN Table X. PSMCON SFR Bit Designations Bit Name Description 7 6 — CMP 5 PSMI 4 TP2 Not Used. AVDD and DVDD Comparator Bit. This is a read-only bit and directly reflects the state of the AVDD and DVDD comparators. Read “1” indicates that both the AVDD and DVDD supplies are above their selected trip points.
ADuC812 MOSI (Master Out, Slave In Pin) The MOSI (master out, slave in) pin is configured as an output line in master mode and an input line in slave mode. The MOSI line on the master (data out) should be connected to the MOSI line in the slave device (data in). The data is transferred as byte wide (8-bit) serial data, MSB first. SCLOCK (Serial Clock I/O Pin) The master serial clock (SCLOCK) is used to synchronize the data being transmitted and received through the MOSI and MISO data lines.
ADuC812 SPIDAT Function SPI Data Register The SPIDAT SFR is written by the user to transmit data over the SPI interface or read by user code to read data just received by the SPI interface. SFR Address Power-On Default Value Bit Addressable F7H 00H No Using the SPI Interface Depending on the configuration of the bits in the SPICON SFR shown in Table XI, the ADuC812 SPI interface will transmit or receive data in a number of possible modes.
ADuC812 I2C* COMPATIBLE INTERFACE The ADuC812 supports a 2-wire serial interface mode that is I2C compatible. The I2C compatible interface shares its pins with the on-chip SPI interface and therefore the user can only enable one or the other interface at any given time (see SPE in Table IX). An application note describing the operation of this interface as implemented is available from the MicroConverter website at www.analog.com/microconverter.
ADuC812 8051 COMPATIBLE ON-CHIP PERIPHERALS This section gives a brief overview of the various secondary peripheral circuits that are also available to the user on-chip. These remaining functions are fully 8051 compatible and are controlled via standard 8051 SFR bit definitions. Parallel I/O Ports 0–3 The ADuC812 uses four input/output ports to exchange data with external devices.
ADuC812 User configuration and control of all Timer operating modes is achieved via three SFRs: TMOD, TCON Control and configuration for Timers 0 and 1. T2CON Control and configuration for Timer 2. TMOD Timer/Counter 0 and 1 Mode Register SFR Address Power-On Default Value Bit Addressable 89H 00H No Gate C/T M1 M0 Gate C/T M1 M0 Table XV. TMOD SFR Bit Designations Bit Name Description 7 Gate 6 C/T 5 4 M1 M0 3 Gate 2 C/T 1 0 M1 M0 Timer 1 Gating Control.
ADuC812 TCON Timer/Counter 0 and 1 Control Register SFR Address Power-On Default Value Bit Addressable 88H 00H Yes TF1 TR1 TF0 IE1* TR0 IT1* IE0* IT0* *These bits are not used in the control of Timer/Counter 0 and 1, but are used instead in the control and monitoring of the external INT0 and INT1 interrupt pins. Table XVI. TCON SFR Bit Designations Bit Name Description 7 TF1 6 TR1 5 TF0 4 TR0 3 IE1 2 IT1 1 IE0 0 IT0 Timer 1 Overflow Flag.
ADuC812 TIMER/COUNTERS 0 AND 1 OPERATING MODES Mode 2 (8-Bit Timer/Counter with Auto Reload) The following paragraphs describe the operating modes for Timer/Counters 0 and 1. Unless otherwise noted, it should be assumed that these modes of operation are the same for Timer 0 as for Timer 1. Mode 2 configures the timer register as an 8-bit counter (TL0) with automatic reload, as shown in Figure 28.
ADuC812 T2CON Timer/Counter 2 Control Register SFR Address Power-On Default Value Bit Addressable C8H 00H Yes TF2 EXF2 RCLK TCLK EXEN2 TR2 CNT2 CAP2 Table XVII. T2CON SFR Bit Designations Bit Name Description 7 TF2 6 EXF2 5 RCLK 4 TCLK 3 EXEN2 2 TR2 1 CNT2 0 CAP2 Timer 2 Overflow Flag. Set by hardware on a Timer 2 overflow. TF2 will not be set when either RCLK = 1 or TCLK = 1. Cleared by user software. Timer 2 External Flag.
ADuC812 Timer/Counter Operation Modes 16-Bit Capture Mode The following paragraphs describe the operating modes for Timer/Counter 2. The operating modes are selected by bits in the T2CON SFR as shown in Table XVIII. In the Capture mode, there are again two options, which are selected by bit EXEN2 in T2CON. If EXEN2 = 0, then Timer 2 is a 16-bit timer or counter that, upon overflowing, sets bit TF2, the Timer 2 overflow bit, that can be used to generate an interrupt.
ADuC812 UART SERIAL INTERFACE The serial port is full-duplex, meaning it can transmit and receive simultaneously. It is also receive-buffered, meaning it can begin receiving a second byte before a previously received byte has been read from the receive register. However, if the first byte still has not been read by the time reception of the second byte is complete, the first byte will be lost. The physical interface to the serial data network is via Pins RXD(P3.0) and TXD(P3.
ADuC812 Mode 0 (8-Bit Shift Register Mode) Mode 2 (9-Bit UART with Fixed Baud Rate) Mode 0 is selected by clearing both the SM0 and SM1 bits in the SFR SCON. Serial data enters and exits through RxD. TxD outputs the shift clock. Eight data bits are transmitted or received. Transmission is initiated by any instruction that writes to SBUF. The data is shifted out of the RxD line. The eight bits are transmitted with the least significant bit (LSB) first, as shown in Figure 32.
ADuC812 Timer 1 Generated Baud Rates Modes 1 and 3 Baud Rate = When Timer 1 is used as the baud rate generator, the baud rates in Modes 1 and 3 are determined by the Timer 1 overflow rate and the value of SMOD as follows: (1 16) × (Timer 2 Overflow Rate) Therefore, when Timer 2 is used to generate baud rates, the timer increments every two clock cycles and not every core machine cycle as before. Therefore, it increments six times faster than Timer 1, and baud rates six times faster are possible.
ADuC812 INTERRUPT SYSTEM The ADuC812 provides a total of nine interrupt sources with two priority levels. The control and configuration of the interrupt system is carried out through three interrupt related SFRs. IE IP IE2 Interrupt Enable Register Interrupt Priority Register Secondary Interrupt Enable Register IE Interrupt Enable Register SFR Address Power-On Default Value Bit Addressable A8H 00H Yes EA EADC ET 2 ES ET1 EX1 ET0 EX0 Table XXII.
ADuC812 IE2 Secondary Interrupt Enable Register SFR Address Power-On Default Value Bit Addressable A9H 00H No — — — — — — EPSMI ESI Table XXIV. IE2 SFR Bit Designations Bit Name Description 7 6 5 4 3 2 1 0 — — — — — — EPSMI ESI Reserved for future use. Reserved for future use. Reserved for future use. Reserved for future use. Reserved for future use. Reserved for future use. Written by user to Enable “1” or Disable “0” power supply monitor interrupt.
ADuC812 ADuC812 HARDWARE DESIGN CONSIDERATIONS This section outlines some of the key hardware design considerations that must be addressed when integrating the ADuC812 into any hardware system. Clock Oscillator The clock source for the ADuC812 can come either from an external source or from the internal clock oscillator. To use the internal clock oscillator, connect a parallel resonant crystal between Pins 32 and 33, and connect a capacitor from each pin to ground as shown below.
ADuC812 If access to more than 64K bytes of RAM is desired, a feature unique to the ADuC812 allows addressing up to 16 MBytes of external RAM simply by adding an additional latch as illustrated in Figure 39. ADuC812 SRAM The best way to implement an external POR function to meet the above requirements involves the use of a dedicated POR chip, such as the ADM809/ADM810 SOT-23 packaged PORs from Analog Devices.
ADuC812 As an alternative to providing two separate power supplies, the user can help keep AV DD quiet by placing a small series resistor and/or ferrite bead between it and DVDD, and then decoupling AVDD separately to ground. An example of this configuration is shown in Figure 44. With this configuration, other analog circuitry (such as op amps, voltage reference, and so on) can be powered from the AVDD supply line as well.
ADuC812 In all of these scenarios, and in more complicated real-life applications, keep in mind the flow of current from the supplies and back to ground. Make sure the return paths for all currents are as close as possible to the paths the currents took to reach their destinations. For example, do not power components on the analog side of Figure 45b with DVDD since that would force return currents from DVDD to flow through AGND.
ADuC812 DOWNLOAD/DEBUG ENABLE JUMPER (NORMALLY OPEN) DVDD DVDD 1k 49 48 47 46 45 44 43 42 41 40 EA 50 PSEN 51 ADC0 DVDD 52 51 ANALOG INPUT DGND 1k 2-PIN HEADER FOR EMULATION ACCESS (NORMALLY OPEN) 39 38 37 AVDD 36 AVDD AGND VREF OUTPUT DVDD DGND 35 DVDD 34 ADuC812 CREF XTAL2 33 VREF XTAL1 32 DAC0 31 DAC1 30 11.
ADuC812 Note that the serial port debugger is fully contained on the ADuC812 device, (unlike ROM monitor type debuggers) and therefore no external memory is needed to enable in-system debug sessions. Single-Pin Emulation Mode Also built into the ADuC812 is a dedicated controller for single-pin in-circuit emulation (ICE) using standard production ADuC812 devices. In this mode, emulation access is gained by connection to a single pin, the EA pin.
ADuC812 TIMING SPECIFICATIONS1, 2, 3 (AV DD = DVDD = 3.0 V or 5.0 V 10%. All specifications TA = TMIN to TMAX, unless otherwise noted.) Parameter Min CLOCK INPUT (External Clock Driven XTAL1) XTAL1 Period tCK tCKL XTAL1 Width Low XTAL1 Width High tCKH XTAL1 Rise Time tCKR tCKF XTAL1 Fall Time tCYC4 ADuC812 Machine Cycle Time 12 MHz Typ Max 83.33 Variable Clock Min Typ Max 62.
ADuC812 Parameter EXTERNAL PROGRAM MEMORY READ CYCLE ALE Pulsewidth tLHLL tAVLL Address Valid to ALE Low Address Hold after ALE Low tLLAX ALE Low to Valid Instruction In tLLIV tLLPL ALE Low to PSEN Low PSEN Pulsewidth tPLPH PSEN Low to Valid Instruction In tPLIV tPXIX Input Instruction Hold after PSEN Input Instruction Float after PSEN tPXIZ Address to Valid Instruction In tAVIV tPLAZ PSEN Low to Address Float tPHAX Address Hold after PSEN High 12 MHz Min Max Variable Clock Min Max 127 43 53 2tCK – 40 t
ADuC812 Parameter EXTERNAL DATA MEMORY READ CYCLE tRLRH RD Pulsewidth Address Valid after ALE Low tAVLL Address Hold after ALE Low tLLAX tRLDV RD Low to Valid Data In Data and Address Hold after RD tRHDX Data Float after RD tRHDZ tLLDV ALE Low to Valid Data In Address to Valid Data In tAVDV ALE Low to RD or WR Low tLLWL tAVWL Address Valid to RD or WR Low RD Low to Address Float tRLAZ tWHLH RD or WR High to ALE High 12 MHz Min Max Min Variable Clock Max 400 43 48 6tCK – 100 tCK – 40 tCK – 35 252 5tCK
ADuC812 Parameter 12 MHz Min Max Variable Clock Min Max Unit EXTERNAL DATA MEMORY WRITE CYCLE WR Pulsewidth tWLWH tAVLL Address Valid after ALE Low Address Hold after ALE Low tLLAX ALE Low to RD or WR Low tLLWL tAVWL Address Valid to RD or WR Low Data Valid to WR Transition tQVWX Data Setup before WR tQVWH tWHQX Data and Address Hold after WR tWHLH RD or WR High to ALE High 400 43 48 200 203 33 433 33 43 6tCK – 100 tCK – 40 tCK – 35 3tCK – 50 4tCK – 130 tCK – 50 7tCK – 150 tCK – 50 tCK – 40 ns ns ns
ADuC812 Parameter Min UART TIMING (Shift Register Mode) tXLXL Serial Port Clock Cycle Time Output Data Setup to Clock tQVXH Input Data Setup to Clock tDVXH tXHDX Input Data Hold after Clock tXHQX Output Data Hold after Clock 700 300 0 50 12 MHz Typ Max Min Variable Clock Typ 1.
ADuC812 Parameter Min Max Unit 2 I C COMPATIBLE INTERFACE TIMING SCLOCK Low Pulsewidth tLOW tHIGH SCLOCK High Pulsewidth Start Condition Hold Time tHD; STA Data Setup Time tSU; DAT tHD; DAT Data Hold time Setup time for Repeated Start tSU; STA Stop Condition Setup Time tSU; STO tBUF Bus Free Time between a STOP Condition and a START Condition Rise Time for Both SCLOCK and SDATA tR tF Fall Time for Both SCLOCK and SDATA tSUP1 Pulsewidth of Spike Suppressed 1.3 0.6 0.6 100 0 0.6 0.
ADuC812 Parameter Min SPI MASTER MODE TIMING (CPHA = 1) tLOW SCLOCK Low Pulsewidth tSH SCLOCK High Pulsewidth Data Output Valid after SCLOCK Edge tDAV Data Input Setup Time before SCLOCK Edge tDSU tDHD Data Input Hold Time after SCLOCK Edge Data Output Fall Time tDF Data Output Rise Time tDR tSR SCLOCK Rise Time tSF SCLOCK Fall Time Typ Max 330 330 50 100 100 10 10 10 10 25 25 25 25 Unit ns ns ns ns ns ns ns ns ns SCLOCK (CPOL = 0) t SL t SH t SR t SF SCLOCK (CPOL = 1) t DAV t DF MSB MOSI M
ADuC812 Parameter Min SPI MASTER MODE TIMING (CPHA = 0) tSL SCLOCK Low Pulsewidth tSH SCLOCK High Pulsewidth Data Output Valid after SCLOCK Edge tDAV Data Output Setup before SCLOCK Edge tDOSU tDSU Data Input Setup Time before SCLOCK Edge Data Input Hold Time after SCLOCK Edge tDHD Data Output Fall Time tDF tDR Data Output Rise Time SCLOCK Rise Time tSR tSF SCLOCK Fall Time Typ Max 330 330 50 150 100 100 10 10 10 10 25 25 25 25 SCLOCK (CPOL = 0) t SL t SH t SF t SR SCLOCK (CPOL = 1) t DAV t DF
ADuC812 Parameter Min SPI SLAVE MODE TIMING (CPHA = 1) tSS SS to SCLOCK Edge tSL SCLOCK Low Pulsewidth SCLOCK High Pulsewidth tSH Data Output Valid after SCLOCK Edge tDAV tDSU Data Input Setup Time before SCLOCK Edge Data Input Hold Time after SCLOCK Edge tDHD Data Output Fall Time tDF tDR Data Output Rise Time SCLOCK Rise Time tSR SCLOCK Fall Time tSF tSFS SS High after SCLOCK Edge Typ Max 0 330 330 50 100 100 10 10 10 10 25 25 25 25 0 Unit ns ns ns ns ns ns ns ns ns ns ns SS t SFS t SS SCLOCK (
ADuC812 Parameter Min SPI SLAVE MODE TIMING (CPHA = 0) tSS SS to SCLOCK Edge tSL SCLOCK Low Pulsewidth SCLOCK High Pulsewidth tSH Data Output Valid after SCLOCK Edge tDAV tDSU Data Input Setup Time before SCLOCK Edge Data Input Hold Time after SCLOCK Edge tDHD Data Output Fall Time tDF tDR Data Output Rise Time SCLOCK Rise Time tSR SCLOCK Fall Time tSF tDOSS Data Output Valid after SS Edge tSFS SS High After SCLOCK Edge Typ Max 0 330 330 50 100 100 10 10 10 10 25 25 25 25 20 0 SS t SFS t SS SCLOCK
ADuC812 OUTLINE DIMENSIONS 14.15 13.90 SQ 13.65 2.45 MAX 1.03 0.88 0.73 27 39 26 40 SEATING PLANE 7.80 REF TOP VIEW 2.10 2.00 1.95 0.23 0.11 VIEW A PIN 1 52 7° 0° 0.25 MIN 10.20 10.00 SQ 9.80 (PINS DOWN) 10° 6° 2° 14 13 1 0.10 COPLANARITY 0.38 0.22 LEAD WIDTH 0.65 BSC LEAD PITCH VIEW A ROTATED 90° CCW COMPLIANT TO JEDEC STANDARDS MO-112-AC-1 Figure 60. 52-Lead Metric Quad Flat Package [MQFP] (S-52-2) Dimensions shown in millimeters 0.30 0.23 0.18 0.60 MAX 0.
ADuC812 REVISION HISTORY 3/13—Rev. E to Rev. F Added EPAD Note to LFCSP Pin Configuration ......................... 6 Added EPAD Note to Pin Function Descriptions Table ............. 8 Updated Outline Dimensions ....................................................... 56 Changes to Ordering Guide .......................................................... 56 4/03—Rev. D to Rev. E Updated Outline Dimensions ....................................................... 56 2/03—Rev. C to Rev. D Added CP-56 Package ...