Datasheet

ADuM1100 Data Sheet
Rev. K | Page 4 of 20
SPECIFICATIONS
ELECTRICAL SPECIFICATIONS—5 V OPERATION
All voltages are relative to their respective ground. 4.5 V ≤ V
DD1
≤ 5.5 V, 4.5 V ≤ V
DD2
≤ 5.5 V. All minimum/maximum specifications
apply over the entire recommended operation range, unless otherwise noted. All typical specifications are at T
A
= 25°C, V
DD1
= V
DD2
= 5 V.
Table 1.
Parameter Symbol Min Typ Max Unit Test Conditions
DC SPECIFICATIONS
Input Supply Current
I
DD1 (Q)
0.3
0.8
mA
V
I
= 0 V or V
DD1
Output Supply Current I
DD2 (Q)
0.01 0.06 mA V
I
= 0 V or V
DD1
Input Supply Current (25 Mbps)
(See Figure 5)
I
DD1 (25)
2.2 3.5 mA 12.5 MHz logic signal frequency
Output Supply Current
1
(25 Mbps)
(See Figure 6)
I
DD2 (25)
0.5 1.0 mA 12.5 MHz logic signal frequency
Input Supply Current (100 Mbps)
(See Figure 5)
I
DD1 (100)
9.0 14 mA 50 MHz logic signal frequency,
ADuM1100BR/ADuM1100UR only
Output Supply Current
1
(100 Mbps)
(See Figure 6)
I
DD2 (100)
2.0 2.8 mA 50 MHz logic signal frequency,
ADuM1100BR/ADuM1100UR only
Input Current I
I
−10 +0.01 +10 µA 0 V ≤ V
IN
≤ V
DD1
Logic High Output Voltage
V
OH
V
DD2
− 0.1
5.0
V
I
O
= −20 μA, V
I
= V
IH
V
DD2
− 0.8 4.6 V I
O
= −4 mA, V
I
= V
IH
Logic Low Output Voltage V
OL
0.0 0.1 V I
O
= 20 μA, V
I
= V
IL
0.03 0.1 V I
O
= 400 μA, V
I
= V
IL
0.3 0.8 V I
O
= 4 mA, V
I
= V
IL
SWITCHING SPECIFICATIONS
For ADuM1100AR
Minimum Pulse Width
2
PW 40 ns C
L
= 15 pF, CMOS signal levels
Maximum Data Rate
3
25 Mbps C
L
= 15 pF, CMOS signal levels
For ADuM1100BR/ADuM1100UR
Minimum Pulse Width
2
PW 6.7 10 ns C
L
= 15 pF, CMOS signal levels
Maximum Data Rate
3
100 150 Mbps C
L
= 15 pF, CMOS signal levels
For All Grades
Propagation Delay Time to Logic Low
Output
4, 5
(See Figure 7)
t
PHL
10.5 18 ns C
L
= 15 pF, CMOS signal levels
Propagation Delay Time to Logic High
Output
4, 5
(See Figure 7)
t
PLH
10.5 18 ns C
L
= 15 pF, CMOS signal levels
Pulse Width Distortion |t
PLH
− t
PHL
|
5
PWD 0.5 2 ns C
L
= 15 pF, CMOS signal levels
Change vs. Temperature
6
3 ps/°C C
L
= 15 pF, CMOS signal levels
Propagation Delay Skew
(Equal Temperature)
5, 7
t
PSK1
8 ns C
L
= 15 pF, CMOS signal levels
Propagation Delay Skew
(Equal Temperature, Supplies)
5, 7
t
PSK2
6 ns C
L
= 15 pF, CMOS signal levels
Output Rise/Fall Time t
R
, t
F
3 ns C
L
= 15 pF, CMOS signal levels
Common-Mode Transient Immunity
at Logic Low/High Output
8
|CM
L
|,
|CM
H
|
25 35 kV/µs V
I
= 0 V or V
DD1
, V
CM
= 1000 V,
transient magnitude = 800 V
Refresh Rate f
r
1.2 Mbps
Input Dynamic Supply Current
9
I
DDI (D)
0.09 mA/Mbps
Output Dynamic Supply Current
9
I
DDO (D)
0.02 mA/Mbps