Datasheet

Data Sheet ADuM1300/ADuM1301
ELECTRICAL CHARACTERISTICS—5 V, 125°C OPERATION
All voltages are relative to their respective ground. 4.5 V ≤ V
DD1
≤ 5.5 V, 4.5 V ≤ V
DD2
≤ 5.5 V; all minimum/maximum specifications apply
over the entire recommended operation range, unless otherwise noted; all typical specifications are at T
A
= 25°C, V
DD1
= V
DD2
= 5 V. These
specifications apply to ADuM1300W and ADuM1301W automotive grade versions.
Table 4.
Parameter Symbol Min Typ Max Unit Test Conditions
DC SPECIFICATIONS
Input Supply Current per Channel, Quiescent I
DDI (Q)
0.50 0.53 mA
Output Supply Current per Channel, Quiescent I
DDO (Q)
0.19 0.24 mA
ADuM1300W, Total Supply Current, Three Channels
1
DC to 2 Mbps
V
DD1
Supply Current I
DD1 (Q)
1.6 2.5 mA DC to 1 MHz logic signal freq.
V
DD2
Supply Current I
DD2 (Q)
0.7 1.0 mA DC to 1 MHz logic signal freq.
10 Mbps (TRWZ Grade Only)
V
DD1
Supply Current I
DD1 (10)
6.5 8.1 mA 5 MHz logic signal freq.
V
DD2
Supply Current
I
DD2 (10)
1.9
2.5
mA
5 MHz logic signal freq.
ADuM1301W, Total Supply Current, Three Channels
1
DC to 2 Mbps
V
DD1
Supply Current I
DD1 (Q)
1.3 2.1 mA DC to 1 MHz logic signal freq.
V
DD2
Supply Current I
DD2 (Q)
1.0 1.4 mA DC to 1 MHz logic signal freq.
10 Mbps (TRWZ Grade Only)
V
DD1
Supply Current I
DD1 (10)
5.0 6.2 mA 5 MHz logic signal freq.
V
DD2
Supply Current I
DD2 (10)
3.4 4.2 mA 5 MHz logic signal freq.
For All Models
Input Currents I
IA
, I
IB
, I
IC
, I
E1
, I
E2
−10 +0.01 +10 µA
0 V ≤ V
IA
, V
IB
, V
IC
≤ V
DD1
or V
DD2
,
0 V ≤ V
E1
, V
E2
≤ V
DD1
or V
DD2
Logic High Input Threshold V
IH
, V
EH
2.0 V
Logic Low Input Threshold V
IL
, V
EL
0.8 V
Logic High Output Voltages V
OAH
, V
OBH
, V
OCH
V
DD1
, V
DD2
− 0.1 5.0 V I
Ox
= −20 µA, V
Ix
= V
IxH
V
DD1
, V
DD2
− 0.4 4.8 V I
Ox
= −4 mA, V
Ix
= V
IxH
Logic Low Output Voltages V
OAL
, V
OBL
, V
OCL
0.0 0.1 V I
Ox
= 20 µA, V
Ix
= V
IxL
0.04 0.1 V I
Ox
= 400 µA, V
Ix
= V
IxL
0.2
0.4
V
I
Ox
= 4 mA, V
Ix
= V
IxL
SWITCHING SPECIFICATIONS
ADuM130xWSRWZ
Minimum Pulse Width
2
PW
1000
ns
C
L
= 15 pF, CMOS signal levels
Maximum Data Rate
3
1 Mbps C
L
= 15 pF, CMOS signal levels
Propagation Delay
4
t
PHL
, t
PLH
50 65 100 ns C
L
= 15 pF, CMOS signal levels
Pulse Width Distortion, |t
PLH
− t
PHL
|
4
PWD 40 ns C
L
= 15 pF, CMOS signal levels
Propagation Delay Skew
5
t
PSK
50 ns C
L
= 15 pF, CMOS signal levels
Channel-to-Channel Matching
6
t
PSKCD
/t
PSKOD
50 ns C
L
= 15 pF, CMOS signal levels
ADuM130xWTRWZ
Minimum Pulse Width
2
PW 100 ns C
L
= 15 pF, CMOS signal levels
Maximum Data Rate
3
10 Mbps C
L
= 15 pF, CMOS signal levels
Propagation Delay
4
t
PHL
, t
PLH
18 27 32 ns C
L
= 15 pF, CMOS signal levels
Pulse Width Distortion, |t
PLH
− t
PHL
|
4
PWD 3 ns C
L
= 15 pF, CMOS signal levels
Change vs. Temperature
5
ps/°C
C
L
= 15 pF, CMOS signal levels
Propagation Delay Skew
5
t
PSK
15 ns C
L
= 15 pF, CMOS signal levels
Channel-to-Channel Matching, Codirectional
Channels
6
t
PSKCD
3 ns C
L
= 15 pF, CMOS signal levels
Channel-to-Channel Matching, Opposing-
Directional Channels
6
t
PSKOD
6 ns C
L
= 15 pF, CMOS signal levels
Rev. J | Page 11 of 32