Datasheet

Data Sheet ADuM1300/ADuM1301
APPLICATIONS INFORMATION
PC BOARD LAYOUT
The ADuM130x digital isolator requires no external interface
circuitry for the logic interfaces. Power supply bypassing is
strongly recommended at the input and output supply pins (see
Figure 14). Bypass capacitors are most conveniently connected
between Pin 1 and Pin 2 for V
DD1
and between Pin 15 and
Pin 16 for V
DD2
. The capacitor value should be between 0.01 µF
and 0.1 µF. The total lead length between both ends of the
capacitor and the input power supply pin should not exceed
20 mm. Bypassing between Pin 1 and Pin 8 and between Pin 9
and Pin 16 should also be considered unless the ground pair on
each package side is connected close to the package.
Figure 14. Recommended Printed Circuit Board Layout
In applications involving high common-mode transients,
care should be taken to ensure that board coupling across the
isolation barrier is minimized. Furthermore, the board layout
should be designed such that any coupling that does occur
equally affects all pins on a given component side. Failure to
ensure this could cause voltage differentials between pins
exceeding the absolute maximum ratings of the device,
thereby leading to latch-up or permanent damage.
See the AN-1109 Application Note for board layout guidelines.
PROPAGATION DELAY-RELATED PARAMETERS
Propagation delay is a parameter that describes the time it takes
a logic signal to propagate through a component. The propagation
delay to a logic low output may differ from the propagation
delay to a logic high output.
Figure 15. Propagation Delay Parameters
Pulse width distortion is the maximum difference between
these two propagation delay values and is an indication of
how accurately the timing of the input signal is preserved.
Channel-to-channel matching refers to the maximum amount
that the propagation delay differs between channels within a
single ADuM130x component.
Propagation delay skew refers to the maximum amount that
the propagation delay differs between multiple ADuM130x
components operating under the same conditions.
DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY
Positive and negative logic transitions at the isolator input
cause narrow (~1 ns) pulses to be sent to the decoder via the
transformer. The decoder is bistable and is therefore either set
or reset by the pulses, indicating input logic transitions. In the
absence of logic transitions at the input for more than ~1 µs, a
periodic set of refresh pulses indicative of the correct input state
are sent to ensure dc correctness at the output. If the decoder
receives no internal pulses for more than about 5 µs, the input
side is assumed to be unpowered or nonfunctional, in which
case the isolator output is forced to a default state (see Table 15)
by the watchdog timer circuit.
The ADuM130x is extremely immune to external magnetic
fields. The limitation on the magnetic field immunity of the
ADuM130x is set by the condition in which induced voltage in
the receiving coil of the transformer is sufficiently large enough
to either falsely set or reset the decoder. The following analysis
defines the conditions under which this may occur. The 3 V
operating condition of the ADuM130x is examined because it
represents the most susceptible mode of operation.
The pulses at the transformer output have an amplitude greater
than 1.0 V. The decoder has a sensing threshold at about 0.5 V,
thus establishing a 0.5 V margin in which induced voltages can be
tolerated. The voltage induced across the receiving coil is given by
V = (−dβ/dt)∑∏r
n
2
; n = 1, 2, … , N
where:
β is magnetic flux density (gauss).
N is the number of turns in the receiving coil.
r
n
is the radius of the n
th
turn in the receiving coil (cm).
Given the geometry of the receiving coil in the ADuM130x and
an imposed requirement that the induced voltage be 50% at
most of the 0.5 V margin at the decoder, a maximum allowable
magnetic field is calculated as shown in Figure 16.
Figure 16. Maximum Allowable External Magnetic Flux Density
V
DD1
GND
1
V
IA
V
IB
V
IC/
V
OC
NC
NC/V
E1
GND
1
V
DD2
GND
2
V
OA
V
OB
V
OC/
V
IC
NC
V
E2
GND
2
03787-015
INPUT (V
Ix
)
OUTPUT (V
Ox
)
t
PLH
t
PHL
50%
50%
03787-016
MAGNETIC FIELD FREQUENCY (Hz)
100
MAXIMUM ALLOWABLE MAGNETIC FLUX
DENSITY (kgauss)
0.001
1M
10
0.01
1k 10k 10M
0.1
1
100M100k
03787-017
Rev. J | Page 25 of 32