Datasheet

ADuM1300/ADuM1301 Data Sheet
ELECTRICAL CHARACTERISTICS—3 V, 105°C OPERATION
All voltages are relative to their respective ground. 2.7 V ≤ V
DD1
≤ 3.6 V, 2.7 V ≤ V
DD2
≤ 3.6 V; all minimum/maximum specifications apply
over the entire recommended operation range, unless otherwise noted; all typical specifications are at T
A
= 25°C, V
DD1
= V
DD2
= 3.0 V.
These specifications do not apply to ADuM1300W and ADuM1301W automotive grade versions.
Table 2.
Parameter Symbol Min Typ Max Unit Test Conditions
DC SPECIFICATIONS
Input Supply Current per Channel, Quiescent I
DDI (Q)
0.26 0.31 mA
Output Supply Current per Channel, Quiescent
I
DDO (Q)
0.11
0.15
mA
ADuM1300 Total Supply Current, Three Channels
1
DC to 2 Mbps
V
DD1
Supply Current I
DD1 (Q)
0.9 1.7 mA DC to 1 MHz logic signal freq.
V
DD2
Supply Current I
DD2 (Q)
0.4 0.7 mA DC to 1 MHz logic signal freq.
10 Mbps (BRW and CRW Grades Only)
V
DD1
Supply Current I
DD1 (10)
3.4 4.9 mA 5 MHz logic signal freq.
V
DD2
Supply Current I
DD2 (10)
1.1 1.6 mA 5 MHz logic signal freq.
90 Mbps (CRW Grade Only)
V
DD1
Supply Current I
DD1 (90)
31 48 mA 45 MHz logic signal freq.
V
DD2
Supply Current I
DD2 (90)
8 13 mA 45 MHz logic signal freq.
ADuM1301 Total Supply Current, Three Channels
1
DC to 2 Mbps
V
DD1
Supply Current I
DD1 (Q)
0.7 1.4 mA DC to 1 MHz logic signal freq.
V
DD2
Supply Current I
DD2 (Q)
0.6 0.9 mA DC to 1 MHz logic signal freq.
10 Mbps (BRW and CRW Grades Only)
V
DD1
Supply Current I
DD1 (10)
2.6 3.7 mA 5 MHz logic signal freq.
V
DD2
Supply Current
I
DD2 (10)
1.8
2.5
mA
5 MHz logic signal freq.
90 Mbps (CRW Grade Only)
V
DD1
Supply Current I
DD1 (90)
24 36 mA 45 MHz logic signal freq.
V
DD2
Supply Current I
DD2 (90)
16 23 mA 45 MHz logic signal freq.
For All Models
Input Currents I
IA
, I
IB
, I
IC
, I
E1
, I
E2
−10 +0.01 +10 µA 0 V ≤ V
IA
, V
IB
, V
IC
≤ V
DD1
or V
DD2
,
0 V ≤ V
E1
, V
E2
≤ V
DD1
or V
DD2
Logic High Input Threshold V
IH
, V
EH
1.6 V
Logic Low Input Threshold V
IL
, V
EL
0.4 V
Logic High Output Voltages V
OAH
, V
OBH
, V
OCH
(V
DD1
or V
DD2
) − 0.1 3.0 V I
Ox
= −20 µA, V
Ix
= V
IxH
(V
DD1
or V
DD2
) − 0.4 2.8 V I
Ox
= −4 mA, V
Ix
= V
IxH
Logic Low Output Voltages V
OAL
, V
OBL
, V
OCL
0.0 0.1 V I
Ox
= 20 µA, V
Ix
= V
IxL
0.04 0.1 V I
Ox
= 400 µA, V
Ix
= V
IxL
0.2
0.4
V
I
Ox
= 4 mA, V
Ix
= V
IxL
SWITCHING SPECIFICATIONS
ADuM130xARW
Minimum Pulse Width
2
PW 1000 ns C
L
= 15 pF, CMOS signal levels
Maximum Data Rate
3
1
Mbps
C
L
= 15 pF, CMOS signal levels
Propagation Delay
4
t
PHL
, t
PLH
50 75 100 ns C
L
= 15 pF, CMOS signal levels
Pulse Width Distortion, |t
PLH
− t
PHL
|
4
PWD 40 ns C
L
= 15 pF, CMOS signal levels
Change vs. Temperature 11 ps/°C C
L
= 15 pF, CMOS signal levels
Propagation Delay Skew
5
t
PSK
50
ns
C
L
= 15 pF, CMOS signal levels
Channel-to-Channel Matching
6
t
PSKCD
/t
PSKOD
50 ns C
L
= 15 pF, CMOS signal levels
Rev. J | Page 6 of 32