Datasheet

ADuM1400/ADuM1401/ADuM1402
Rev. D | Page 4 of 24
Parameter Symbol Min Typ Max Unit Test Conditions
SWITCHING SPECIFICATIONS
ADuM140xARW
Minimum Pulse Width
3
PW 1000 ns C
L
= 15 pF, CMOS signal levels
Maximum Data Rate
4
1 Mbps C
L
= 15 pF, CMOS signal levels
Propagation Delay
5
t
PHL
, t
PLH
50 65 100 ns C
L
= 15 pF, CMOS signal levels
Pulse Width Distortion, |t
PLH
− t
PHL
|
5
PWD 40 ns C
L
= 15 pF, CMOS signal levels
Propagation Delay Skew
6
t
PSK
50 ns C
L
= 15 pF, CMOS signal levels
Channel-to-Channel Matching
7
t
PSKCD/OD
50 ns C
L
= 15 pF, CMOS signal levels
ADuM140xBRW
Minimum Pulse Width
3
PW 100 ns C
L
= 15 pF, CMOS signal levels
Maximum Data Rate
4
10 Mbps C
L
= 15 pF, CMOS signal levels
Propagation Delay
5
t
PHL
, t
PLH
20 32 50 ns C
L
= 15 pF, CMOS signal levels
Pulse Width Distortion, |t
PLH
− t
PHL
|
5
PWD 3 ns C
L
= 15 pF, CMOS signal levels
Change vs. Temperature 5 ps/°C C
L
= 15 pF, CMOS signal levels
Propagation Delay Skew
6
t
PSK
15 ns C
L
= 15 pF, CMOS signal levels
Channel-to-Channel Matching,
Codirectional Channels
7
t
PSKCD
3 ns C
L
= 15 pF, CMOS signal levels
Channel-to-Channel Matching,
Opposing-Directional Channels
7
t
PSKOD
6 ns C
L
= 15 pF, CMOS signal levels
ADuM140xCRW
Minimum Pulse Width
3
PW 8.3 11.1 ns C
L
= 15 pF, CMOS signal levels
Maximum Data Rate
4
90 120 Mbps C
L
= 15 pF, CMOS signal levels
Propagation Delay
5
t
PHL
, t
PLH
18 27 32 ns C
L
= 15 pF, CMOS signal levels
Pulse Width Distortion, |t
PLH
− t
PHL
|
5
PWD 0.5 2 ns C
L
= 15 pF, CMOS signal levels
Change vs. Temperature 3 ps/°C C
L
= 15 pF, CMOS signal levels
Propagation Delay Skew
6
t
PSK
10 ns C
L
= 15 pF, CMOS signal levels
Channel-to-Channel Matching,
Codirectional Channels
7
t
PSKCD
2 ns C
L
= 15 pF, CMOS signal levels
Channel-to-Channel Matching,
Opposing-Directional Channels
7
t
PSKOD
5 ns C
L
= 15 pF, CMOS signal levels
For All Models
Output Disable Propagation Delay
(High/Low to High Impedance)
t
PHZ
, t
PLH
6 8 ns C
L
= 15 pF, CMOS signal levels
Output Enable Propagation Delay
(High Impedance to High/Low
t
PZH
, t
PZL
6 8 ns C
L
= 15 pF, CMOS signal levels
Output Rise/Fall Time (10% to 90%) t
R
/t
F
2.5 ns C
L
= 15 pF, CMOS signal levels
Common-Mode Transient Immunity
at Logic High Output
8
|CM
H
| 25 35 kV/μs
V
Ix
= V
DD1
/V
DD2
, V
CM
= 1000 V,
transient magnitude = 800 V
Common-Mode Transient Immunity
at Logic Low Output
8
|CM
L
| 25 35 kV/μs
V
Ix
= 0 V, V
CM
= 1000 V,
transient magnitude = 800 V
Refresh Rate f
r
1.2 Mbps
Input Dynamic Supply Current per Channel
9
I
DDI (D)
0.19 mA/Mbps
Output Dynamic Supply Current per Channel
9
I
DDO (D)
0.05 mA/Mbps