Datasheet

ADV212
Rev. B | Page 13 of 44
EXTERNAL DMA MODE—FIFO READ, BURST MODE
Table 9.
Parameter Mnemonic Min Typ Max Unit
DREQ Pulse Width
1
DREQ
PULSE
1 JCLK
2
15 JCLK
2
ns
RD to DREQ Deassert (DR × PULS = 0)
t
DREQ
RTN
2.5 JCLK
2
3.5 × JCLK + 7.5
2
ns
DACK to RD Setup
t
DACK
SU
0 ns
RD to Data Valid
t
RD
2.5 9.7 ns
Data Hold t
HD
2.5 ns
RD Assert Pulse Width
RD
LOW
1.5 JCLK
2
ns
RD Deassert Pulse Width
RD
HIGH
1.5 JCLK
2
ns
RD Deassert to Next DREQ
t
DREQ
WAIT
2.5 JCLK
2
3.5 × JCLK + 7.5
2
ns
RD Deassert to DACK Deassert
t
RD_DACK
0 ns
1
Applies to assigned DMA channel if EDMOD0 or EDMOD1 <14:11> is programmed to a nonzero value.
2
For a definition of JCLK, see Figure 32.
DREQ
DACK
HDATA
0 1 13 14 15
t
DACK
SU
t
DREQ
WAIT
t
DREQ
PULSE
t
RD
t
HD
t
RD_DACK
RD
RD
LOW
RD
HIGH
06389-025
Figure 16. Burst Read Cycle for
DREQ
/
DACK
DMA Mode for Assigned DMA Channel
(EMOD0/EDMOD1[14:11] Not Programmed to a Value of 0
DREQ
DACK
HDATA
0 1 13 14 15
t
DACK
SU
t
DREQ
WAIT
t
DREQ
RTN
t
RD
t
HD
t
RD_DACK
RD
RD
LOW
RD
HIGH
06389-026
Figure 17. Burst Read Cycle for
DREQ
/
DACK
DMA Mode for Assigned DMA Channel
(EMOD0/EDMOD1[14:11] Programmed to a Value of 0000)
DREQ
DACK
RDFB
t
DACK
SU
t
HD
t
DREQ
WAIT
HDATA
0 1 13 14 15
t
RD
t
DREQ
RTN
t
RD_DACK
06389-027
Figure 18. Burst Read Cycle for Fly-By DMA Mode