Datasheet
ADV212
Rev. B | Page 17 of 44
RAW PIXEL MODE TIMING
Table 12.
Parameter Mnemonic Min Typ Max Unit
VCLK to PIXELDATA Valid Delay (PIXELDATA Output)
1
VDATA
TD
12 ns
PIXELDATA Setup to Rising VCLK (PIXELDATA Input) VDATA
SU
4 ns
PIXELDATA Hold from Rising VCLK (PIXELDATA Input) VDATA
HD
4 ns
VCLK to VRDY Valid Delay VRDY
TD
12 ns
VFRM Setup to Rising VCLK (VFRAME Input) VFRM
SU
3 ns
VFRM Hold from Rising VCLK (VFRAME Input) VFRM
HD
4 ns
VCLK to VFRM Valid Delay (VFRAME Output) VFRM
TD
12 ns
VSTRB Setup to Rising VCLK VSTRB
SU
4 ns
VSTRB Hold from Rising VCLK VSTRB
HD
3 ns
1
PIXELDATA is the actual data on the VDATA bus; pins and bus width depend on it but timing does not.
RAW PIXEL MODE—ENCODE
VCLK
PIXEL 1 PIXEL 2 PIXEL 3
VSTRB
HD
VFRM
SU
VFRM
HD
VRDY
TD
VSTRB
SU
VDATA
HD
VDATA
SU
VFRM (IN)
VSTRB (IN)
VRDY (OUT)
PIXELDATA (IN)
RAW PIXEL MODE—DECODE
VCLK
PIXEL 1 PIXEL 2
PIXEL 3
VSTRB
SU
VSTRB
HD
VFRM
TD
VDATA
TD
VRDY
TD
VFRM (OUT)
VSTRB (IN)
VRDY (OUT)
PIXELDATA (OUT)
06389-031
Figure 28. Raw Pixel Modes