Datasheet

ADV212

Rev. B | Page 28 of 44

INTERNAL REGISTERS

This section describes the internal registers of the ADV212.

DIRECT REGISTERS

The ADV212 has 16 direct registers, as listed in Table 18.

The direct registers are accessed over the ADDR[3:0],

HDATA[31:0],

, and

ACK

pins.

The host must first initialize the direct registers before

any application-specific operation can be implemented.

Table 18. Direct Registers

Address Name Description

0x00 Pixel Pixel FIFO access register

0x01 Code Compressed code stream access register

0x02 AT TR Attribute FIFO access register

0x03 Reserved Reserved

0x04 CMDSTA Command stack

0x05 EIRQIE External interrupt enabled

0x06 EIRQFLG External interrupt flags

0x07 SWFLAG Software flag register

0x08 BUSMODE Bus mode configuration register

0x09 MMODE Miscellaneous mode register

0x0A Stage Staging register

0x0B IADDR Indirect address register

0x0C IDATA Indirect data register

0x0D Boot Boot mode register

0x0E PLL_HI PLL control register, high byte

0x0F PLL_LO PLL control register, low byte