Datasheet

ADV212
Rev. B | Page 35 of 44
DECODE—MULTICHIP MASTER/SLAVE
In a master/slave configuration, it is expected that the master
HVF outputs are connected to the slave HVF inputs and that
each SCOMM5 pin is connected to the same GPIO on the host.
In a slave/slave configuration, the common HVF for both
ADV212s is generated by an external house sync, and each
SCOMM5 is connected to the same GPIO output on the host.
SWIRQ1, Software Interrupt 1 in the EIRQIE register, must be
unmasked on both devices to enable multichip mode.
DATA[31:0] HDATA[31:0]
ADDR[3:0] ADDR[3:0]
CS CS
RD RD
WR
WE
ACK ACK
IRQ
CS
RD
WR
ACK
IRQ
DREQ
DACK
IRQ
DREQ
DREQ
FIELD
VSYNC
HSYNC
DACK DACK
GPIO SCOMM[5]
VCLK
1080i
VIDEO OUT
MCLK
VDATA[11:2]
32-BIT HOST CPU
10-BIT SD/HD
VIDEO
ENCODER
ADV212_1_MASTER
SCOMM[5]
HDATA[31:0]
ADDR[3:0]
CS
RD
WE
ACK
IRQ
FIELD
VSYNC
HSYNC
DREQ
DACK
VCLK
MCLK
V
DATA[11:2]
ADV212_2_SLAVE
CLKIN
Y[9:0]
C[9:0]
CbCr
CbCr
Y Y
74.25MHz
OSC
06389-003
Figure 34. Decode—Multichip Master/Slave Application