Datasheet

ADV212
Rev. B | Page 40 of 44
JDATA INTERFACE
Figure 39 shows a typical configuration using JDATA with a dedicated JDATA output, 16-bit host, and 10-bit CCIR 656.
16-BIT
HOST CPU
FPGA
ADV212
HDATA[15:0]DATA[15:0]
ADV7189
IRQIRQ
ADDR[3:0]ADDR[3:0]
P[19:10]VDATA[11:2]
FIELDFIELD
VSVSYNC
HS
LLC1
HSYNC
MCLK
27MHz
OSC
VCLK
VIDEO IN
YCrCb
CSCS
JDATA[7:0]
HOLD
VALID
RD
RD
WE
WE
ACKACK
06389-008
Figure 39. JDATA Application