Datasheet

ADV212
Rev. B | Page 5 of 44
CLOCK AND RESET SPECIFICATIONS
Table 3.
Parameter Mnemonic Min Typ Max Unit
MCLK Period t
MCLK
13.3 100 ns
MCLK Frequency f
MCLK
10 75.18 MHz
MCLK Width Low t
MCLKL
6 ns
MCLK Width High t
MCLKH
6 ns
VCLK Period t
VCLK
13.4 50 ns
VCLK Frequency f
VCLK
20 74.60 MHz
VCLK Width Low t
VCLKL
5 ns
VCLK Width High t
VCLKH
5 ns
RESET Width Low
t
RESET
5 MCLK cycles
1
1
For a definition of MCLK, see Figure 32.
MCLK
VCLK
t
MCLK
t
MCLKH
t
MCLKL
t
VCLKH
t
VCLKL
t
VCLK
06389-010
Figure 2. Input Clock