Datasheet

ADV212
Rev. B | Page 8 of 44
DREQ/DACK DMA MODE—SINGLE FIFO WRITE OPERATION
Table 6.
Parameter Mnemonic Min Typ Max Unit
DREQ Pulse Width DREQ
PULSE
1 JCLK
1
15 JCLK
1
ns
DACK Assert to Subsequent DREQ Delay
t
DREQ
2.5 JCLK
1
3.5 × JCLK + 8.5
1
ns
WE to DACK Setup
t
WE
SU
0 ns
Data to DACK Deassert Setup
t
SU
2 ns
Data to DACK Deassert Hold
t
HD
2 ns
DACK Assert Pulse Width DACK
LOW
2 JCLK
1
ns
DACK Deassert Pulse Width DACK
HIGH
2 JCLK
1
ns
WE Hold After DACK Deassert
t
WE
HD
0 ns
WE Assert to FSRQ Deassert (FIFO Full) WFSRQ
1.5 JCLK
1
2.5 × JCLK + 7.5
1
ns
DACK to DREQ Deassert (DR × PULS = 0)
t
DREQ
RTN
2.5 JCLK
1
3.5 × JCLK + 9.0
1
ns
1
For a definition of JCLK, see Figure 32.
WE
DACK
DREQ
HDATA
3210
DREQ
PULSE
t
DREQ
DACK
HIGH
DACK
LOW
t
WE
SU
t
SU
t
HD
t
WE
HD
06389-013
Figure 5. Single Write for
DREQ
/
DACK
DMA Mode for Assigned DMA Channel
(EDMOD0/EDMOD1[14:1] Not Programmed to a Value of 0000)
WE
DACK
DREQ
HDATA
0 1 2
t
DREQ
RTN
DACK
HIGH
DACK
LOW
t
WE
SU
t
SU
t
HD
t
WE
HD
06389-014
Figure 6. Single Write for
DREQ
/
DACK
DMA Mode for Assigned DMA Channel
(EDMOD0/EDMOD1[14:11] Programmed to a Value of 0000)