Datasheet

ADV212
Rev. B | Page 9 of 44
WEFB
DACK
DREQ
HDATA
0 1 2
DREQ
PULSE
t
DREQ
DACK
HIGH
DACK
LOW
t
WE
SU
t
SU
t
HD
t
WE
HD
06389-015
Figure 7. Single Write Cycle for Fly-By DMA Mode
(
DREQ
Pulse Width Is Programmable)
RD
FCS0
HDATA
1 2
FIFO NOT FULL
WFSRQ
FIFO FULL
NOT WRITTEN TO FIFO
FSRQ0
0
t
SU
t
HD
06389-021
Figure 8. Single Write Access for DCS DMA Mode