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Table Of Contents

FEATURES
APPLICATIONS
FUNCTIONAL BLOCK DIAGRAM
TABLE OF CONTENTS
- REVISION HISTORY
SPECIFICATIONS
- 2.8 V SPECIFICATIONS
- 2.8 V TIMING SPECIFICATIONS
- 3.3 V SPECIFICATIONS
- 3.3 V TIMING SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
- ESD CAUTION
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
GENERAL DESCRIPTION
- DATA PATH DESCRIPTION
- INTERNAL FILTER RESPONSE
TYPICAL PERFORMANCE CHARACTERISTICS
FEATURES
- COLOR BAR GENERATION
- SQUARE PIXEL MODE
- COLOR SIGNAL CONTROL
- BURST SIGNAL CONTROL
- NTSC PEDESTAL CONTROL
- PIXEL TIMING DESCRIPTION
  - 8-Bit YCrCb Mode
- SUBCARRIER RESET
- REAL-TIME CONTROL
- POWER-ON RESET
- SCH PHASE MODE
- MPU PORT DESCRIPTION
- REGISTER ACCESSES
REGISTER PROGRAMMING
- SUBADDRESS REGISTER (SR7–SR0)
- REGISTER SELECT (SR5–SR0)
- MODE REGISTER 1 (MR1)
- MODE REGISTER 2 (MR2)
- MODE REGISTER 3 (MR3)
- MODE REGISTER 4 (MR4)
- TIMING MODE REGISTER 0 (TR0)
- TIMING MODE REGISTER 1 (TR1)
- SUBCARRIER FREQUENCY REGISTERS 3–0
- SUBCARRIER PHASE REGISTER
- CLOSED CAPTIONING EVEN FIELD DATA REGISTERS 1–0
- CLOSED CAPTIONING ODD FIELD DATA REGISTERS 1–0
- NTSC PEDESTAL/PAL TELETEXT CONTROL REGISTERS 3–0
- TELETEXT REQUEST CONTROL REGISTER (TC07)
- CGMS_WSS REGISTER 0 (C/W0)
- CGMS_WSS REGISTER 1 (C/W1)
- CGMS_WSS REGISTER 2 (C/W2)
APPENDIX 1—BOARD DESIGN AND LAYOUT CONSIDERATIONS
- GROUND PLANES
- POWER PLANES
- SUPPLY DECOUPLING
- DIGITAL SIGNAL INTERCONNECT
- ANALOG SIGNAL INTERCONNECT
APPENDIX 2—CLOSED CAPTIONING
APPENDIX 3—COPY GENERATION MANAGEMENT SYSTEM (CGMS)
- FUNCTION OF CGMS BITS
APPENDIX 4—WIDE SCREEN SIGNALING (WSS)
- FUNCTION OF WSS BITS
APPENDIX 5—TELETEXT
- TELETEXT INSERTION
- TELETEXT PROTOCOL
APPENDIX 6—WAVEFORMS
- NTSC WAVEFORMS (WITH PEDESTAL)
- NTSC WAVEFORMS (WITHOUT PEDESTAL)
- PAL WAVEFORMS
- Pb Pr WAVEFORMS
APPENDIX 7—OPTIONAL OUTPUT FILTER
APPENDIX 8—RECOMMENDED REGISTER VALUES
OUTLINE DIMENSIONS
- ORDERING GUIDE

Chip Scale PAL/NTSC Video Encoder with

Advanced Power Management

ADV7174/ADV7179

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700 www.analog.com

FEATURES

ITU-R

BT601/BT656 YCrCb to PAL/NTSC video encoder

High quality 10-bit video DACs

SSAF™ (super sub-alias filter)

Advanced power management features

CGMS (copy generation management system)

WSS (wide screen signaling)

NTSC M, PAL N

, PAL B/D/G/H/I, PAL-M

, PAL 60

Single 27 MHz clock required (×2 oversampling)

Macrovision 7.1 (ADV7174 only)

80 dB video SNR

32-bit direct digital synthesizer for color subcarrier

Multistandard video output support:

Composite (CVBS)

Component S-video (Y/C)

Video input data port supports:

CCIR-656 4:2:2 8-bit parallel input format

Programmable simultaneous composite and S-video or RGB

(SCART)/YPbPr video outputs

Programmable luma filters low-pass [PAL/NTSC] notch,

extended SSAF, CIF, and QCIF

Programmable chroma filters (low-pass [0.65 MHz, 1.0 MHz,

1.2 MHz, and 2.0 MHz], CIF, and QCIF)

Programmable VBI (vertical blanking interval)

Programmable subcarrier frequency and phase

Programmable LUMA delay

Individual on/off control of each DAC

CCIR and square pixel operation

Integrated subcarrier locking to external video source

Color signal control/burst signal control

Interlaced/noninterlaced operation

Complete on-chip video timing generator

Programmable multimode master/slave operation

Closed captioning support

Teletext insertion port (PAL-WST)

On-board color bar generation

On-board voltage reference

2-wire serial MPU interface (I

C® compatible and fast I

Single-supply 2.8 V and 3.3 V operation

Small 40-lead 6 mm × 6 mm LFCSP package

−40°C to +85°C at 3.3 V

−20°C to +85°C at 2.8 V

APPLICATIONS

Portable video applications

Mobile phones

Digital still cameras

FUNCTIONAL BLOCK DIAGRAM

C MPU PORT

SCLOCK SDATA ALSB

HSYNC

FIELD/VSYNC

BLANK

CLOCK

GND

DACA(PIN29)

REF

SET

COMP

ADV7174/ADV7179

COLOR

DATA

P7–P0

SCRESET/RTC

DACB(PIN28)

DACC(PIN24)

RESET

TELETEXT

INSERTION

BLOCK

YUV TO

RBG

MATRIX

VOLTAGE

REFERENCE

CIRCUIT

REAL-TIME

CONTROL

CIRCUIT

10-BIT

DAC

10-BIT

DAC

10-BIT

DAC

CGMS AND WSS

INSERTION

BLOCK

ADD

SYNC

ADD

BURST

INTER-

POLATOR

SIN/COS

DDS BLOCK

VIDEO TIMING

GENERATOR

PROGRAMMABLE

LUMINANCE

FILTER

PROGRAMMABLE

CHROMINANCE

FILTER

INTER-

POLATOR

POWER

MANAGEMENT

CONTROL

(SLEEP MODE)

YCrCb

YUV

MATRIX

4:2:2 TO

4:4:4

INTER-

POLATOR

TTXREQ TTX

02980-A-001

Figure 1.

ITU-R and CCIR are used interchangeably in this document (ITU-R has replaced CCIR recommendations).

Throughout the document, N is referenced to PAL – Combination – N.

ADV7174 only.

The Macrovision anticopy process is licensed for noncommercial home use only, which is its sole intended use in the device. Contact the sales office for the latest

Macrovision version available.

Summary of content (52 pages)

PAGE 1
Chip Scale PAL/NTSC Video Encoder with Advanced Power Management ADV7174/ADV7179 FEATURES Programmable subcarrier frequency and phase ITU-R1 BT601/BT656 YCrCb to PAL/NTSC video encoder Programmable LUMA delay High quality 10-bit video DACs Individual on/off control of each DAC SSAF™ (super sub-alias filter) CCIR and square pixel operation Advanced power management features Integrated subcarrier locking to external video source CGMS (copy generation management system) Color signal control/burst signal contro
PAGE 2
ADV7174/ADV7179 TABLE OF CONTENTS Specifications..................................................................................... 4 Mode 3: Master/Slave Option HSYNC, BLANK, FIELD . 24 2.8 V Specifications ...................................................................... 4 Power-On Reset .......................................................................... 25 2.8 V Timing Specifications ........................................................ 5 SCH Phase Mode ............................
PAGE 3
ADV7174/ADV7179 Appendix 3—Copy Generation Management System (CGMS) ............................................................................................................42 Function of CGMS Bits ..............................................................42 Appendix 4—Wide Screen Signaling (WSS) ...............................43 Function of WSS Bits ..................................................................43 Appendix 5—Teletext ...............................................................
PAGE 4
ADV7174/ADV7179 SPECIFICATIONS 2.8 V SPECIFICATIONS VAA = 2.8 V, VREF = 1.235 V, RSET = 150 Ω. All specifications TMIN to TMAX 1 , unless otherwise noted. Table 1.
PAGE 5
ADV7174/ADV7179 2.8 V TIMING SPECIFICATIONS VAA = 2.8 V, VREF = 1.235 V, RSET = 150 Ω. All specifications TMIN to TMAX 1 , unless otherwise noted. Table 2.
PAGE 6
ADV7174/ADV7179 3.3 V SPECIFICATIONS VAA = 3.0 V–3.6 V 1 , VREF = 1.235 V, RSET = 150 Ω. All specifications TMIN to TMAX 2 , unless otherwise noted. Table 3.
PAGE 7
ADV7174/ADV7179 3.3 V TIMING SPECIFICATIONS VAA = 3.0 V–3.6 V 1 , VREF = 1.235 V, RSET = 150 Ω. All specifications TMIN to TMAX 2 , unless otherwise noted. Table 4.
PAGE 8
ADV7174/ADV7179 t5 t3 t3 SDATA t6 SCLOCK t2 t7 t4 t8 02980-0A-002 t1 Figure 2. MPU Port Timing Diagram CLOCK t9 t12 HSYNC, FIELD/VSYNC, BLANK PIXEL INPUT DATA Cb Y Cr Y t11 CONTROL O/PS Cb Y t13 HSYNC, FIELD/VSYNC, BLANK 02980-A-003 CONTROL I/PS S t10 t14 Figure 3. Pixel and Control Data Timing Diagram TTXREQ t16 CLOCK t17 t18 4 CLOCK CYCLES 4 CLOCK CYCLES 4 CLOCK CYCLES Figure 4. Teletext Timing Diagram Rev.
PAGE 9
ADV7174/ADV7179 ABSOLUTE MAXIMUM RATINGS Table 5. Parameter VAA to GND Voltage on Any Digital Input Pin Storage Temperature (TS) Junction Temperature (TJ) Lead Temperature Soldering, 10 sec Analog Outputs to GND1 θJA2 Rating 4V GND – 0.5 V to VAA + 0.5 V −65°C to +150°C 150°C 260°C GND – 0.5 V to VAA 30°C/W Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device.
PAGE 10
ADV7174/ADV7179 P2 P1 P0 TTX TTXREQ SCRESET/ RTC RSET 39 P3 GND 40 P4 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 38 37 36 35 34 33 32 31 PIN 1 INDICATOR 30 VREF 29 DAC A P5 3 28 DAC B 4 27 VAA 26 GND CLOCK 1 VAA 2 P6 ADV7174/ADV7179 LFCSP P7 5 GND 6 TOP VIEW (Not to Scale) GND 7 25 VAA 24 DAC C 15 16 17 18 19 20 02980-A-005 14 GND 13 RESET 12 GND GND 11 VAA SCLOCK GND 21 ALSB SDATA VAA 10 BLANK COMP 22 HSYNC 23 FIELD/VSYNC 8 GND 9 GND
PAGE 11
ADV7174/ADV7179 GENERAL DESCRIPTION The ADV7174/ADV7179 is an integrated digital video encoder that converts digital CCIR-601 4:2:2 8-bit component video data into a standard analog baseband television signal compatible with worldwide standards. The on-board SSAF (super sub-alias filter) with extended luminance frequency response and sharp stop-band attenuation enables studio quality video playback on modern TVs, giving optimal horizontal line resolution.
PAGE 12
ADV7174/ADV7179 Table 7. Luminance Internal Filter Specifications Filter Type Low-Pass (NTSC) Low-Pass (PAL) Notch (NTSC) Notch (PATL) Extended (SSAF) CIF QCIF Filter Selection MR04 MR03 MR02 0 0 0 Pass-Band Ripple (dB) 3 dB Bandwidth (MHz) Stop-Band Cutoff (MHz) Stop-Band Attenuation (dB) 0.091 4.157 7.37 −56 0 0 1 0.15 4.74 7.96 −64 0 0 1 1 1 0 0 1 0 0.015 0.095 0.051 6.54 6.24 6.217 8.3 8.0 8.0 −68 −66 −61 1 1 0 1 1 0 0.018 Monotonic 3.0 1.5 7.06 7.15 −61 −50 Table 8.
PAGE 13
ADV7174/ADV7179 0 0 –10 –10 –20 –20 MAGNITUDE (dB) –30 –40 –60 –70 –40 –50 02980-A-006 –50 –30 0 2 4 6 8 FREQUENCY (MHz) 10 02980-A-009 MAGNITUDE (dB) TYPICAL PERFORMANCE CHARACTERISTICS –60 –70 12 0 2 0 0 –10 –10 –20 –20 –30 –40 –30 –40 0 2 4 6 8 FREQUENCY (MHz) 10 –60 –70 12 0 Figure 7. PAL Low-Pass Luma Filter 2 4 6 8 FREQUENCY (MHz) 10 12 Figure 10.
PAGE 14
0 0 –10 –10 –20 –20 MAGNITUDE (dB) –30 –40 –60 –70 –40 –50 02980-A-012 –50 –30 0 2 4 6 8 FREQUENCY (MHz) 10 02980-A-015 MAGNITUDE (dB) ADV7174/ADV7179 –60 –70 12 0 0 0 –10 –10 –20 –20 –30 –40 12 –30 –40 0 2 4 6 8 FREQUENCY (MHz) 10 –60 –70 12 0 Figure 13. 1.3 MHz Low-Pass Chroma Filter 2 4 6 8 FREQUENCY (MHz) 10 12 Figure 16. 2.
PAGE 15
ADV7174/ADV7179 0 –10 –30 –40 –50 02980-A-018 MAGNITUDE (dB) –20 –60 –70 0 2 4 6 8 FREQUENCY (MHz) 10 12 Figure 18. QCIF Chroma Filter Rev.
PAGE 16
ADV7174/ADV7179 FEATURES COLOR BAR GENERATION REAL-TIME CONTROL The ADV7174/ADV7179 can be configured to generate 100/ 7.5/75/7.5 color bars for NTSC or 100/0/75/0 for PAL color bars. These are enabled by setting MR17 of Mode Register 1 to Logic 1. Together with the SCRESET/RTC pin and Bits MR22 and MR21 of Mode Register 2, the ADV7174/ADV7179 can be used to lock to an external video source.
PAGE 17
ADV7174/ADV7179 CLOCK COMPOSITE VIDEO (e.g., VCR OR CABLE) SCRESET/RTC VIDEO DECODER (e.g.
PAGE 18
ADV7174/ADV7179 ANALOG VIDEO EAV CODE Y SAV CODE C F 0 0 X 8 1 8 1 Y r F 0 0 Y 0 0 0 0 ANCILLARY DATA (HANC) 4 CLOCK NTSC/PAL M SYSTEM (525 LlNES/60Hz) 8 1 8 1 F 0 0 X C Y C Y C Y C Y C b r b 0 0 0 0 F 0 0 Y b r 0 F F A A A 0 F F B B B 4 CLOCK 268 CLOCK 1440 CLOCK 4 CLOCK 4 CLOCK PAL SYSTEM (625 LINES/50Hz) 280 CLOCK 02980-A-020 INPUT PIXELS 1440 CLOCK END OF ACTIVE VIDEO LINE START OF ACTIVE VIDEO LINE Figure 20.
PAGE 19
ADV7174/ADV7179 DISPLAY 622 623 DISPLAY VERTICAL BLANK 624 625 1 2 3 4 5 6 7 21 22 23 H V EVEN FIELD F ODD FIELD DISPLAY 309 310 DISPLAY VERTICAL BLANK 311 312 313 314 315 316 317 318 319 320 335 334 336 H ODD FIELD EVEN FIELD Figure 22. Timing Mode 0 (PAL Master Mode) ANALOG VIDEO H F 02980-A-023 F 02980-A-022 V V Figure 23. Timing Mode 0 Data Transitions (Master Mode) Rev.
PAGE 20
ADV7174/ADV7179 Mode 1: Slave Option HSYNC, BLANK, FIELD input when HSYNC is low indicates a new frame, i.e., vertical retrace. The BLANK signal is optional. When the BLANK input is disabled, the ADV7174/ADV7179 automatically blanks all normally blank lines as per CCIR-624. Mode 1 is illustrated in Figure 24 (NTSC) and Figure 25 (PAL). (Timing Register 0 TR0 = X X X X X 0 1 0) In this mode, the ADV7174/ADV7179 accepts horizontal SYNC and odd/even FIELD signals.
PAGE 21
ADV7174/ADV7179 Mode 1: Master Option HSYNC, BLANK, FIELD (Timing Register 0 TR0 = X X X X X 0 1 1) In this mode, the ADV7174/ADV7179 can generate horizontal SYNC and odd/even FIELD signals. A transition of the FIELD input when HSYNC is low indicates a new frame, i.e., vertical retrace. The BLANK signal is optional. When the BLANK input is disabled, the ADV7174/ADV7179 automatically blanks all normally blank lines as per CCIR-624.
PAGE 22
ADV7174/ADV7179 Mode 2: Slave Option HSYNC, VSYNC, BLANK transition when HSYNC is high indicates the start of an even field. The BLANK signal is optional. When the BLANK input is disabled, the ADV7174/ADV7179 automatically blanks all normally blank lines as per CCIR-624. Mode 2 is illustrated in Figure 27 (NTSC) and Figure 28 (PAL). (Timing Register 0 TR0 = X X X X X 1 0 0) In this mode, the ADV7174/ADV7179 accepts horizontal and vertical SYNC signals.
PAGE 23
ADV7174/ADV7179 Mode 2: Master Option HSYNC, VSYNC, BLANK BLANK input is disabled, the ADV7174/ADV7179 automatically blanks all normally blank lines as per CCIR-624. Mode 2 is illustrated in Figure 27 (NTSC) and Figure 28 (PAL). Figure 29 illustrates the HSYNC, BLANK, and VSYNC for an even-toodd field transition relative to the pixel data. Figure 30 illustrates the HSYNC, BLANK, and VSYNC for an odd-toeven field transition relative to the pixel data.
PAGE 24
ADV7174/ADV7179 Mode 3: Master/Slave Option HSYNC, BLANK, FIELD that is, vertical retrace. The BLANK signal is optional. When the BLANK input is disabled, the ADV7174/ADV7179 automatically blanks all normally blank lines as per CCIR-624. Mode 3 is illustrated in Figure 31 (NTSC) and Figure 32 (PAL). (Timing Register 0 TR0 = X X X X X 1 1 0 or X X X X X 1 1 1) In this mode, the ADV7174/ADV7179 accepts or generates horizontal SYNC and odd/even FIELD signals.
PAGE 25
ADV7174/ADV7179 1 Resetting the SCH phase every four or eight fields avoids the accumulation of SCH phase error and results in very minor SCH phase jumps at the start of the 4- or 8-field sequence. Resetting the SCH phase should not be done if the video source does not have stable timing or the ADV7174/ADV7179 is configured in RTC mode (MR21 = 1 and MR22 = 1). Under these conditions (unstable video), the subcarrier phase reset should be enabled (MR22 = 0 and MR21 = 1), but no reset applied.
PAGE 26
ADV7174/ADV7179 Frequency Registers 1, 2, and 3. The subcarrier frequency registers should not be accessed independently. Figure 35 illustrates an example of data transfer for a read sequence and the start and stop conditions. Figure 36 shows bus write and read sequences. Stop and start conditions can be detected at any stage during the data transfer. If these conditions are asserted out of sequence with normal read and write operations, they cause an immediate jump to the idle condition.
PAGE 27
ADV7174/ADV7179 REGISTER PROGRAMMING This section describes the configuration of each register, including the subaddress register, mode registers, subcarrier frequency registers, the subcarrier phase register, timing registers, closed captioning extended data registers, closed captioning data registers, and NTSC pedestal control registers. Figure 37 shows the various operations under the control of the subaddress register. Zero should always be written to SR7–SR6.
PAGE 28
ADV7174/ADV7179 MODE REGISTER 0 (MR0) Bits: Address: MR07 – MR00 SR4–SR0 = 00H Figure 38 shows the various operations under the control of Mode Register 0. This register can be read from as well as written to. MR06 MR05 MR04 CHROMA FILTER SELECT MR07 MR06 MR05 0 0 0 1.3 MHz LOW-PASS FILTER 0 0 1 0.65 MHz LOW-PASS FILTER 0 1 0 1.0 MHz LOW-PASS FILTER 0 1 1 2.
PAGE 29
ADV7174/ADV7179 MODE REGISTER 1 (MR1) Bits: Address: MR17–MR10 SR4–SR0 = 01H Figure 39 shows the various operations under the control of Mode Register 1. This register can be read from as well as written to.
PAGE 30
ADV7174/ADV7179 MODE REGISTER 2 (MR2) Bits: Address: MR27–MR20 SR4–SR0 = 02H Mode Register 2 is an 8-bit-wide register. Figure 40 shows the various operations under the control of Mode Register 2. This register can be read from as well as written to.
PAGE 31
ADV7174/ADV7179 MODE REGISTER 3 (MR3) Bits: Address: MR37–MR30 SR4–SR0 = 03H Mode Register 3 is an 8-bit-wide register. Figure 41 shows the various operations under the control of Mode Register 3.
PAGE 32
ADV7174/ADV7179 MODE REGISTER 4 (MR4) Bits: Address: MR47–MR40 SR4–SR0 = 04H Mode Register 4 is an 8-bit-wide register. Figure 42 shows the various operations under the control of Mode Register 4.
PAGE 33
ADV7174/ADV7179 TIMING MODE REGISTER 0 (TR0) Bits: Address: TR07–TR00 SR4–SR0 = 07H Figure 43 shows the various operations under the control of Timing Register 0. This register can be read from as well as written to.
PAGE 34
ADV7174/ADV7179 TIMING MODE REGISTER 1 (TR1) Bits: Address: TR17–TR10 SR4–SR0 = 08H Timing Register 1 is an 8-bit-wide register. Figure 44 shows the various operations under the control of Timing Register 1. This register can be read from as well written to. This register can be used to adjust the width and position of the master mode timing signals.
PAGE 35
ADV7174/ADV7179 SUBCARRIER FREQUENCY REGISTERS 3–0 Bits: Address: FSC3–FSC0 SR4–SR00 = 09H–0CH These 8-bit-wide registers are used to set up the subcarrier frequency. The value of these registers is calculated by using the following equation: No. of Subcarrier Frequency Values in One Line of Video Line 32 ×2 * No. of 27 MHz Clock Cycles in One Video Line * Rounded to the nearest integer. For example, in NTSC mode, Subcarrier Frequency Value = 227.
PAGE 36
ADV7174/ADV7179 CLOSED CAPTIONING ODD FIELD DATA REGISTERS 1–0 Bits: Subaddress: CCD15–CCD0 SR4–SR0 = 10H–11H BYTE 1 BYTE 0 CCD15 CCD14 CCD13 CCD12 CCD11 CCD10 CCD7 CCD6 CCD5 CCD4 CCD3 CCD2 CCD9 CCD1 CCD8 CCD0 002980-A-046 These 8-bit-wide registers are used to set up the closed captioning data bytes on odd fields. Figure 47 shows how the high and low bytes are set up in the registers. Figure 47.
PAGE 37
ADV7174/ADV7179 TELETEXT REQUEST CONTROL REGISTER (TC07) Bits: Address: TC07–TC00 SR4–SR0 = 19H Teletext control register is an 8-bit-wide register (see Figure 50). Table 17. Teletext Request Control Register Bit Name TTXREQ Rising Edge Control Bit No. TC07–TC04 TTXREQ Falling Edge Control TC03–TC00 Description These bits control the position of the rising edge of TTXREQ. It can be programmed from 0 CLOCK cycles to a maximum of 15 CLOCK cycles (see Figure 50).
PAGE 38
ADV7174/ADV7179 CGMS_WSS REGISTER 1 (C/W1) Bits: Address : C/W17–C/W10 SR4–SR0 = 17H CGMS_WSS Register 1 is an 8-bit-wide register. Figure 52 shows the operations under the control of this register. C/W16 C/W15 C/W14 C/W13 C/W12 C/W17 – C/W16 C/W15 – C/W10 CGMS DATA BITS CGMS/WSS DATA BITS C/W11 C/W10 02980-A-051 C/W17 Figure 52. CGMS_WSS Register 1 Table 19. C/W1 Bit Description Bit Name CGMS/WSS Data Bits Bit No.
PAGE 39
ADV7174/ADV7179 APPENDIX 1—BOARD DESIGN AND LAYOUT CONSIDERATIONS POWER PLANES The ADV7174/ADV7179 is a highly integrated circuit containing both precision analog and high speed digital circuitry. It has been designed to minimize interference effects on the integrity of the analog circuitry by the high speed digital circuitry. It is imperative that these same design and layout techniques be applied to the system-level design so that high speed, accurate performance is achieved.
PAGE 40
ADV7174/ADV7179 SUPPLY DECOUPLING ANALOG SIGNAL INTERCONNECT For optimum performance, bypass capacitors should be installed using the shortest leads possible, consistent with reliable operation, to reduce the lead inductance. Best performance is obtained with 0.1 μF ceramic capacitor decoupling. Each group of VAA pins on the ADV7174/ADV7179 must have at least one 0.1 μF decoupling capacitor to GND. These capacitors should be placed as close to the device as possible.
PAGE 41
ADV7174/ADV7179 APPENDIX 2—CLOSED CAPTIONING ADV7174/ADV7179. All pixel inputs are ignored during Lines 21 and 284. FCC Code of Federal Regulations (CFR) 47 Section 15.119 and EIA-608 describe the closed captioning information for Lines 21 and 284. The ADV7174/ADV7179 supports closed captioning, conforming to the standard television synchronizing waveform for color transmission. Closed captioning is transmitted during the blanked active line time of Line 21 of the odd fields and Line 284 of even fields.
PAGE 42
ADV7174/ADV7179 APPENDIX 3—COPY GENERATION MANAGEMENT SYSTEM (CGMS) C/W17 = C15, C/W20 = C0, C/W21 = C1, C/W22 = C2, C/W23 = C3, C/W24 = C4, C/W25 = C5, C/W26 = C6, C/W27 = C7. If Bit C/W04 is set to a Logic 1, the last six bits, C19–C14, which comprise the 6-bit CRC check sequence, are calculated automatically on the ADV7174/ADV7179 based on the lower 14 bits (C0–C13) of the data in the data registers and output with the remaining 14 bits to form the complete 20 bits of the CGMS data.
PAGE 43
ADV7174/ADV7179 APPENDIX 4—WIDE SCREEN SIGNALING (WSS) The ADV7174/ADV7179 supports WSS, conforming to the standard. WSS data is transmitted on Line 23. WSS data can only be transmitted when the ADV7174/ ADV7179 is configured in PAL mode. The WSS data is 14 bits long, the function of each of these bits is as shown below. The WSS data is preceded by a run-in sequence and a start code (see Figure 58).
PAGE 44
ADV7174/ADV7179 APPENDIX 5—TELETEXT TELETEXT INSERTION TELETEXT PROTOCOL tPD is the time needed by the ADV7174/ADV7179 to interpolate input data on TTX and insert it onto the CVBS or Y outputs, such that it appears tSYNTTXOUT = 10.2 μs after the leading edge of the horizontal signal. Time TTXDEL is the pipeline delay time by the source that is gated by the TTXREQ signal in order to deliver TTX data. The relationship between the TTX bit clock (6.
PAGE 45
ADV7174/ADV7179 APPENDIX 6—WAVEFORMS NTSC WAVEFORMS (WITH PEDESTAL) 130.8 IRE PEAK COMPOSITE 1268.1mV 100 IRE REF WHITE 1048.4mV BLACK LEVEL BLANK LEVEL 387.6mV 334.2mV –40 IRE SYNC LEVEL 48.3mV REF WHITE 1048.4mV 02980-A-060 714.2mV 7.5 IRE 0 IRE Figure 61. NTSC Composite Video Levels 100 IRE 7.5 IRE 0 IRE BLACK LEVEL BLANK LEVEL –40 IRE SYNC LEVEL 387.6mV 334.2mV 48.3mV 02980-A-061 714.2mV Figure 62. NTSC Luma Video Levels PEAK CHROMA 963.8mV 629.
PAGE 46
ADV7174/ADV7179 NTSC WAVEFORMS (WITHOUT PEDESTAL) 130.8 IRE PEAK COMPOSITE 1289.8mV 100 IRE REF WHITE 1052.2mV 0 IRE BLANK/BLACK LEVEL 338mV –40 IRE SYNC LEVEL 52.1mV 02980-A-064 714.2mV Figure 65. NTSC Composite Video Levels 100 IRE REF WHITE 1052.2mV 0 IRE BLANK/BLACK LEVEL SYNC LEVEL –40 IRE 338mV 52.1mV 02980-A-065 714.2mV Figure 66. NTSC Luma Video Levels PEAK CHROMA 978mV 694.9mV (p-p) 286mV (p-p) 650mV BLANK/BLACK LEVEL PEAK CHROMA 02980-A-066 299.3mV 0mV Figure 67.
PAGE 47
ADV7174/ADV7179 PAL WAVEFORMS 1288.6mV PEAK COMPOSITE 1051mV REF WHITE 351mV BLANK/BLACK LEVEL 51mV SYNC LEVEL 02980-A-068 700mV Figure 69. PAL Composite Video Levels REF WHITE 1051mV 351mV BLANK/BLACK LEVEL 51mV SYNC LEVEL 02980-A-069 700mV Figure 70. PAL Luma Video Levels PEAK CHROMA 989.7mV 672mV (p-p) 300mV (p-p) 650mV BLANK/BLACK LEVEL PEAK CHROMA 02980-A-070 317.7mV 0mV Figure 71.
PAGE 48
ADV7174/ADV7179 BLACK BLUE RED MAGENTA GREEN +334mV CYAN WHITE +505mV YELLOW BLACK BLUE RED MAGENTA GREEN CYAN WHITE YELLOW Pb Pr WAVEFORMS +505mV +423mV +171mV BETACAM LEVEL BETACAM LEVEL +82mV 0mV 0mV 0mV 0mV –82mV –171mV –05mV –423mV –505mV Figure 76. NTSC 100% Color Bars, No Pedestal Pr Levels BLACK BLUE RED MAGENTA GREEN +309mV CYAN WHITE +467mV YELLOW BLACK BLUE RED MAGENTA GREEN CYAN YELLOW Figure 73.
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ADV7174/ADV7179 APPENDIX 7—OPTIONAL OUTPUT FILTER 22pF 0 10 20 MAGNITUDE (dB) If an output filter is required for the CVBS, Y, UV, chroma, and RGB outputs of the ADV7174/ADV7179, the filter shown in Figure 79 can be used. Plots of the filter characteristics are shown in Figure 80. An output filter is not required if the outputs of the ADV7174/ADV7179 are connected to most analog monitors or analog TVs. However, if the output signals are applied to a system where sampling is used (e.g.
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ADV7174/ADV7179 APPENDIX 8—RECOMMENDED REGISTER VALUES The ADV7174/ADV7179 registers can be set depending on the user standard required. The power-on reset values can be found in Figure 37. The following examples give the various register formats for several video standards. In each case, the output is set to composite output with all DACs powered up and with the input control disabled.
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ADV7174/ADV7179 Table 27. NTSC (FSC = 3.5795454 MHz) Table 26. PAL-60 (FSC = 4.
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ADV7174/ADV7179 OUTLINE DIMENSIONS 6.00 BSC SQ 0.60 MAX 0.60 MAX PIN 1 INDICATOR TOP VIEW 0.50 BSC 5.75 BSC SQ 0.50 0.40 0.30 12° MAX 1.00 0.85 0.80 PIN 1 INDICATOR 31 30 40 1 4.25 4.10 SQ 3.95 BOTTOM VIEW 21 20 10 11 0.25 MIN 4.50 REF 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM SEATING PLANE 0.30 0.23 0.18 0.20 REF COPLANARITY 0.08 COMPLIANT TO JEDEC STANDARDS MO-220-VJJD-2 Figure 81.