Multiformat SDTV Video Decoder with Fast Switch Overlay Support ADV7184 FEATURES Multiformat video decoder supports NTSC (J/M/4.43), PAL (B/D/G/H/I/M/N), SECAM Integrates four 54 MHz, 10-bit ADCs SCART fast blank support Clocked from a single 28.
ADV7184 TABLE OF CONTENTS Features .............................................................................................. 1 Global Status Registers .............................................................. 23 Applications....................................................................................... 1 Standard Definition Processor (SDP).......................................... 24 General Description .........................................................................
ADV7184 User Sub Map...............................................................................99 Digital Inputs.............................................................................110 PCB Layout Recommendations ................................................. 109 XTAL and Load Capacitor Values Selection .........................110 Analog Interface Inputs........................................................... 109 Typical Circuit Connection .............................................
ADV7184 INTRODUCTION STANDARD DEFINITION PROCESSOR (SDP) The ADV7184 is a high quality, single chip, multiformat video decoder that automatically detects and converts PAL, NTSC, and SECAM standards in the form of composite, S-video, and component video into a digital ITU-R BT.656 format. The ADV7184 is capable of decoding a large selection of baseband video signals in composite, S-video, and component formats.
ADV7184 SPECIFICATIONS ELECTRICAL CHARACTERISTICS AVDD = 3.15 V to 3.45 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.71 V to 1.89 V, nominal input range 1.6 V. Operating temperature range, unless otherwise noted. Table 1.
ADV7184 VIDEO SPECIFICATIONS At AVDD = 3.15 V to 3.45 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.71 V to 1.89 V (operating temperature range, unless otherwise noted). Table 2.
ADV7184 THERMAL SPECIFICATIONS Table 4. Parameter Junction-to-Case Thermal Resistance Junction-to-Ambient Thermal Resistance (Still Air) Symbol θJC θJA Test Conditions 4-layer PCB with solid ground plane 4-layer PCB with solid ground plane Min Typ 7.6 38.1 Max Unit °C/W °C/W TIMING SPECIFICATIONS AVDD = 3.15 V to 3.45 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.71 V to 1.89 V (operating temperature range, unless otherwise noted). Table 5.
ADV7184 TIMING DIAGRAMS t3 t5 t3 SDA t1 t6 t4 t7 t2 05479-002 SCLK t8 Figure 2. I2C Timing t9 t10 OUTPUT LLC1 t11 t12 OUTPUT LLC2 t13 05479-003 t14 OUTPUTS P0 TO P15, VS, HS, FIELD, SFL Figure 3. Pixel Port and Control Output Timing OE t15 t16 Figure 4. OE Timing Rev.
ADV7184 ABSOLUTE MAXIMUM RATINGS Table 6. Parameter AVDD to AGND DVDD to DGND PVDD to AGND DVDDIO to DGND DVDDIO to AVDD PVDD to DVDD DVDDIO to PVDD DVDDIO to DVDD AVDD to PVDD AVDD to DVDD Digital Inputs Voltage to DGND Digital Output Voltage to DGND Analog Inputs to AGND Maximum Junction Temperature (TJ max) Storage Temperature Range Infrared Reflow Soldering (20 sec) Rating 4V 2.2 V 2.2 V 4V −0.3 V to +0.3 V −0.3 V to +0.3 V −0.3 V to +2 V −0.3 V to +2 V −0.3 V to +2 V −0.3 V to +2 V −0.
ADV7184 AIN12 AIN6 SOY RESET TEST7 ALSB SDA SCLK TEST4 TEST0 DGND DVDD P15 P14 P13 P12 TEST6 TEST1 OE FIELD PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 VS 1 60 AIN5 59 AIN11 DGND 3 58 AIN4 DVDDIO 4 57 AIN10 P11 5 56 AGND P10 6 55 CAPC2 P9 7 54 CAPC1 53 AGND 52 CML DVDD 10 51 REFOUT INT 11 50 AVDD SFL 12 49 CAPY2 TEST2 13 48 CAPY1 DGND 14 47 AGND DVDDIO 15 46 AIN3 TEST8 16 45 AIN9 TE
ADV7184 Pin No. 67 68 66 Mnemonic SDA SCLK ALSB Type I/O I I 64 RESET I 27 LLC1 O 26 LLC2 O 29 XTAL I 28 XTAL1 O 36 PWRDN I 79 OE I 37 12 ELPF SFL I O 63 SOY I 51 REFOUT O 52 CML O 48, 49 CAPY1, CAPY2 CAPC1, CAPC2 I Description I2C Port Serial Data Input/Output. I2C Port Serial Clock Input. Maximum clock rate of 400 kHz. This pin selects the I2C address for the ADV7184. ALSB set to Logic 0 sets the address for a write to 0x40; set to Logic 1 sets the address to 0x42.
ADV7184 ANALOG FRONT END RGB_IP_SEL PRIM_MODE[3:0] ADC_SW_MAN_EN INTERNAL MAPPING FUNCTIONS SDM_SEL[1:0] AIN1 AIN7 AIN2 AIN8 AIN3 AIN9 AIN4 AIN10 AIN5 AIN11 AIN6 AIN12 AIN3 AIN9 AIN4 AIN10 AIN5 AIN11 AIN6 AIN12 AIN2 AIN8 AIN5 AIN11 AIN6 AIN12 AIN4 1 ADC0 1 ADC1_SW[3:0] 0 ADC1 1 ADC2_SW[3:0] 0 ADC2 1 AIN4 ADC0_SW[3:0] 0 ADC3_SW[3:0] 0 AIN7 ADC3 Figure 6. Internal Pin Connections Rev.
ADV7184 ANALOG INPUT MUXING Recommended Input Muxing The ADV7184 has an integrated analog muxing section that allows connecting more than one source of video signal to the decoder. Figure 6 outlines the overall structure of the input muxing provided in the ADV7184. A maximum of 12 CVBS inputs can be connected and decoded by the ADV7184, meaning that the sources must be connected to adjacent pins on the IC, as seen in Figure 5.
ADV7184 Table 9. Input Channel Switching Using INSEL [3:0] INSEL [3:0], Input Selection, Address 0x00 [3:0] The INSEL bits allow the user to select the input channel and format. Depending on the PCB connections, only a subset of the INSEL modes is valid. INSEL [3:0] not only switches the analog input muxing, but also configures ADV7184 to process composite (CVBS), S-video (Y/C), or component (YPbPr/RGB) format signals.
ADV7184 Table 10. Input Channel Assignments Input Channel AIN7 AIN1 AIN8 AIN2 AIN9 AIN3 AIN10 AIN4 AIN11 AIN5 AIN12 AIN6 Pin No. 41 42 43 44 45 46 57 58 59 60 61 62 Recommended Input Muxing Control—INSEL [3:0] SCART1-B YC1-Y YPrPb1-Y SCART2-CVBS SCART1-R YC2-Y YPrPb2-Y SCART1-G YC3-Y YPrPb2-Pb CVBS7 CVBS1 CVBS8 CVBS2 CVBS9 CVBS3 CVBS10 CVBS4 CVBS11 CVBS5 Not available CVBS6 YC1-C YPrPb1-Pb YC2-C YPrPb1-Pr SCART2-B SCART1-CVBS SCART2-R YC3-C YPrPb2-Pr SCART2-G Table 11.
ADV7184 ADC_SW_MAN_EN, Manual Input Muxing Enable, Address 0xC4 [7] ADC0_SW [3:0], ADC0 Mux Configuration, Address 0xC3 [3:0] ADC1_SW [3:0], ADC1 Mux Configuration, Address 0xC3 [7:4] ADC2_SW [3:0], ADC2 Mux Configuration, Address 0xC4 [3:0] ADC3_SW [3:0], ADC3 Mux Configuration, Address 0xF3 [7:4] AA_FILT_EN [1], Address 0xF3 [1] 0 (default)—The filter on Channel 1 is disabled. 1—The filter on Channel 1 is enabled. AA_FILT_EN [2], Address 0xF3 [2] 0 (default)—The filter on Channel 2 is disabled.
ADV7184 The alpha blend factor is selected with the I2C signal MAN_ALPHA_VAL [6:0]. Overlay is not possible in fixed alpha blending mode. • • Dynamic Switching (Fast Mux). The FB pin can be used to select the source. This enables dynamic multiplexing between the CVBS and RGB sources. With default settings, when Logic 1 is applied to the FB pin, the RGB source is selected; when Logic 0 is applied to the FB pin, the CVBS source is selected.
ADV7184 FAST BLANK (FB PIN) SIGNAL CONDITIONING CLAMPING AND DECIMATION ADC0 R G B I2C CONTROL TIMING EXTRACTION VIDEO PROCESSING YPrPb SUBPIXEL BLENDER OUTPUT FORMATTER ADC1 ADC2 SIGNAL CONDITIONING CLAMPING AND DECIMATION RGB ≥ YPrPb CONVERSION ADC3 05479-009 CVBS FAST BLANK POSITION RESOLVER Figure 9. Fast Blanking Configuration RGB SOURCE Fast Blank Edge Shaping FB_EDGE_SHAPE [2:0], Address 0xEF [2:0] 100% CVBS SOURCE 50% CONTRAST SANDCASTLE CVBS SOURCE 100% Table 13.
ADV7184 Fast Blank and Contrast Reduction Programmable Thresholds FB PIN The internal fast blank and contrast reduction signals are resolved from the trilevel FB signal using two comparators, as shown in Figure 11. To facilitate compliance with different input level standards, the reference level to these comparators is programmable via FB_LEVEL [1:0] and CNTR_LEVEL [1:0]. The resulting thresholds are given in Table 15.
ADV7184 FB_INV, Address 0xED [3], Write Only The interpretation of the polarity of the signal applied to the FB pin can be changed using FB_INV. 0 (default)—The fast blank pin is active high. 1—The fast blank pin is active low. Readback of FB Pin Status FB_STATUS [3:0], Address 0xED [7:4] FB_STATUS [3:0] is a readback value that provides the system information on the status of the FB pins, as shown in Table 16.
ADV7184 GLOBAL CONTROL REGISTERS Register control bits listed in this section affect the whole chip. PWRDN_ADC_2, Address 0x3A [1] POWER-SAVING MODES 0 (default)—The ADC is in normal operation. Power-Down PDBP, Address 0x0F [2] 1—ADC2 is powered down. PWRDN_ADC_3, Address 0x3A [0] The digital core of the ADV7184 can be shut down by using the PWRDN pin or the PWRDN bit. The PDBP bit determines which of the two controls has the higher priority. The default is to give the pin (PWRDN) priority.
ADV7184 strength controls are provided by the DR_STR_S, DR_STR_C, and DR_STR bits of Register 0xF4. Drive Strength Selection (Clock) DR_STR_C [1:0], Address 0xF4 [3:2] 0 (default)—The output drivers are enabled. The DR_STR_C [1:0] bits can be used to select the strength of the clock signal output driver (LLC pin). For more information, refer to the Drive Strength Selection (Sync) and the Drive Strength Selection (Data) sections. 1—The output drivers are three-stated.
ADV7184 GLOBAL STATUS REGISTERS Three registers provide summary information about the video decoder: Status Register 1, Status Register 2, and Status Register 3. These registers contain status bits that report operational information to the user. Status Register 1 [7:0], Address 0x10 [7:0] This read-only register provides information about the internal status of the ADV7184.
ADV7184 STANDARD DEFINITION PROCESSOR (SDP) STANDARD DEFINITION PROCESSOR MACROVISION DETECTION DIGITIZED CVBS DIGITIZED Y (YC) DIGITIZED CVBS DIGITIZED C (YC) VBI DATA RECOVERY LUMA DIGITAL FINE CLAMP CHROMA DIGITAL FINE CLAMP CHROMA DEMOD STANDARD AUTODETECTION SLLC CONTROL LUMA FILTER LUMA GAIN CONTROL LUMA RESAMPLE SYNC EXTRACT LINE LENGTH PREDICTOR RESAMPLE CONTROL CHROMA FILTER CHROMA GAIN CONTROL CHROMA RESAMPLE LUMA 2D COMB AV CODE INSERTION CHROMA 2D COMB VIDEO DATA OUTPUT MEA
ADV7184 SYNC PROCESSING GENERAL SETUP The ADV7184 extracts syncs embedded in the video data stream. There is currently no support for external HS/VS inputs. The sync extraction is optimized to support imperfect video sources, such as videocassette recorders with head switches. The actual algorithm used employs a coarse detection based on a threshold crossing, followed by a more detailed detection using an adaptive interpolation algorithm.
ADV7184 AD_SEC525_EN, SECAM 525 Autodetect Enable, Address 0x07 [7] AD_NTSC_EN, NTSC Autodetect Enable, Address 0x07 [1] 0 (default)—Disables the autodetection of a 525-line system with a SECAM style, FM-modulated color component. 0—Disables the autodetection of standard NTSC. 1—Enables autodetection. AD_SECAM_EN, SECAM Autodetect Enable, Address 0x07 [6] 0—Disables the autodetection of SECAM. 1 (default)—Enables autodetection.
ADV7184 The TIME_WIN signal is based on a line-to-line evaluation of the horizontal synchronization pulse of the incoming video. It reacts quickly. Lock-Related Controls Lock information is presented to the user through Bits [1:0] of Status Register 1. See the Status Register 1 [7:0], Address 0x10 [7:0] section. Figure 13 outlines the signal flow and the controls that are available to influence how the lock status information is generated.
ADV7184 FSCLE, FSC Lock Enable, Address 0x51 [7] The FSCLE bit allows the user to choose if the status of the color subcarrier loop is taken into account when the overall lock status is determined and presented via Bits [1:0] in Status Register 1. The FSCLE bit must be set to 0 when operating in YPrPb (component) mode to generate a reliable horizontal lock status bit (INST_HLOCK). 0 (default)—Makes the overall lock status dependent on the horizontal sync lock.
ADV7184 SD_OFF_CB [7:0], SD Offset Cb Channel, Address 0xE1 [7:0] DEF_Y [5:0], Default Value Y, Address 0x0C [7:2] If the ADV7184 loses lock to the incoming video signal or if there is no input signal, the DEF_Y [5:0] bits allow the user to specify a default luma value to be output. The register is used if These bits allow the user to adjust the hue of the picture by selecting the offset for the Cb channel. There is a functional overlap with the HUE [7:0] bits. Table 31.
ADV7184 DEF_VAL_AUTO_EN, Default Value Automatic Enable, Address 0x0C [1] This bit enables the automatic use of the default values for Y, Cr, and Cb when the ADV7184 cannot lock to the video signal. 0—Disables free-run mode. If the decoder is unlocked, it outputs noise. 1 (default)—Enables free-run mode. A colored screen set by the user-programmable Y, Cr, and Cb values is displayed when the decoder loses lock. CLAMP OPERATION The input video is ac-coupled into the ADV7184 through a 0.1 μF capacitor.
ADV7184 S-video type sources, and a second for nonstandard composite signals. The YSH filter responses also include a set of notches for PAL and NTSC. However, it is recommended to use the comb filters for Y/C separation. DCT [1:0], Digital Clamp Timing, Address 0x15 [6:5] The clamp timing register determines the time constant of the digital fine-current clamp circuitry.
ADV7184 In automatic mode, the system preserves the maximum possible bandwidth for good CVBS sources (because they can successfully be combed) and for luma components of YPrPb and Y/C sources (because they need not be combed). For poor quality signals, the system selects from a set of proprietary shaping filter responses that complements comb filter operation to reduce visual artifacts. The control logic is shown in Figure 15. Table 36.
ADV7184 COMBINED Y ANTIALIAS, S-VHS LOW-PASS FILTERS, Y RESAMPLE WYSFMOVR, Wideband Y-Shaping Filter Override, Address 0x18 [7] 0 –30 –40 –50 1 (default)—Enables manual selection of a wideband filter via WYSFM [4:0]. –60 WYSFM [4:0], Wideband Y-Shaping Filter Mode, Address 0x18 [4:0] –70 0 2 4 6 8 10 12 FREQUENCY (MHz) Figure 16.
ADV7184 COMBINED Y ANTIALIAS, NTSC NOTCH FILTERS, Y RESAMPLE COMBINED C ANTIALIAS, C SHAPING FILTER, C RESAMPLER 0 0 –10 –20 ATTENUATION (dB) –30 –40 –50 –30 –40 –50 05479-019 –60 –70 –20 0 2 4 6 8 10 –60 12 05479-020 AMPLITUDE (dB) –10 0 FREQUENCY (MHz) 1 2 3 4 5 6 FREQUENCY (MHz) Figure 19. Y NTSC Notch Filter Responses Figure 20.
ADV7184 The minimum supported amplitude of the input video is determined by the ability of the ADV7184 to retrieve horizontal and vertical timing and to lock to the color burst, if present. GAIN OPERATION The gain control within the ADV7184 is done on a purely digital basis. The input ADCs support a 10-bit range, mapped into a 1.6 V analog voltage range. Gain correction takes place after the digitization in the form of a digital multiplier. There are separate gain control units for luma and chroma data.
ADV7184 Luma Gain LAGC [2:0], Luma Automatic Gain Control, Address 0x2C [6:4] LG [11:0]/LMG [11:0], Luma Gain/Luma Manual Gain, Address 0x2F [3:0], Address 0x30 [7:0] The luma automatic gain control mode bits select the mode of operation for the gain control in the luma path. Analog Devices internal parameters can be used to customize the peak white gain control. Contact an Analog Devices representative for more information. Luma manual gain [11:0] are dual-function bits.
ADV7184 BETACAM, Enable BETACAM Levels, Address 0x01 [5] PW_UPD, Peak White Update, Address 0x2B [0] If YPrPb data is routed through the ADV7184, the automatic gain control modes can target different video input levels, as outlined in Table 44. Note that the BETACAM bit is valid only if the input mode is YPrPb (component). The BETACAM bit sets the target value for AGC operation. The peak white and average video algorithms determine the gain based on measurements taken from the active video.
ADV7184 Chroma Gain CAGC [1:0], Chroma Automatic Gain Control, Address 0x2C [1:0] For example, freezing the automatic gain loop results in a readback value of 0x47A for the CMG [11:0] bits. 1. Convert the readback value to decimal: 0x47A = 1146d 2. Apply Equation 4 to convert the readback value: 1146/1024 = 1.12 These two bits select the basic mode of operation for automatic gain control in the chroma path. Table 45.
ADV7184 CHROMA TRANSIENT IMPROVEMENT (CTI) block must be enabled via the CTI_EN bit. The settings of the CTI_AB_EN bit are as follows: The signal bandwidth allocated for chroma is typically much smaller than that of luminance. With older devices, this was a valid way to fit a color video signal into a given overall bandwidth because the human eye is less sensitive to chrominance than to luminance. 0—Disables the CTI alpha blender. 1 (default)—Enables the CTI alpha blender.
ADV7184 DNR_EN, Digital Noise Reduction Enable, Address 0x4D [5] 0—Bypasses DNR (disables it). 1 (default)—Enables DNR on the luma data. DNR_TH [7:0], DNR NoiseThreshold, Address 0x50 [7:0] The DNR1 block is positioned before the luma peaking block. The DNR_TH [7:0] value is an unsigned, 8-bit number that determines the maximum edge that is interpreted as noise and therefore blanked from the luma data.
ADV7184 CCMN [2:0], Chroma Comb Mode NTSC, Address 0x38 [5:3] Table 52.
ADV7184 PAL Comb Filter Settings CCMP [2:0], Chroma Comb Mode PAL, Address 0x39 [5:3] Used for PAL B/G/H/I/D, PAL M, PAL Combinational N, PAL 60, and NTSC 4.43 CVBS inputs. Table 56. CCMP [2:0] Function PSFSEL [1:0], Split Filter Selection PAL, Address 0x19 [1:0] PFSEL [1:0] selects how much of the overall signal bandwidth is fed to the combs. A wide bandwidth split filter eliminates dot crawl, but shows imperfections on diagonal lines. The opposite is true for a narrow bandwidth split filter. Table 54.
ADV7184 Vertical Blank Control Each vertical blank control register (Addresses 0xEB and 0xEC) has the same meaning for the following bit settings: 00—Early by one line. 10—Delayed by one line. 11—Delayed by two lines. 01 (default)—Described in each register section. PVBIOCCM [1:0], PAL VBI Odd Field Chroma Comb Mode, Address 0xEC [3:2] These bits control the first combed line after VBI on PAL odd field (chroma comb). 01 (default)—ITU-R BT.
ADV7184 In a 16-bit output interface where Y and Cr/Cb are delivered via separate data buses, the AV code is over the whole 16 bits. The SD_DUP_AV bit allows the user to replicate the AV codes on both buses; therefore, the full AV sequence can be found on the Y data bus and on the Cr/Cb data bus (see Figure 25). Refer to the BL_C_VBI, Blank Chroma During VBI, Address 0x04 [2] section for information on the chroma path. 0 (default)—The AV codes are in single fashion (to suit 8-bit interleaved data output).
ADV7184 RANGE, Range Selection, Address 0x04 [0] CTA [2:0], Chroma Timing Adjust, Address 0x27 [5:3] AV codes (as per ITU-R BT.656, formerly known as CCIR 656) consist of a fixed header made up of 0xFF and 0x00 values. These two values are reserved and therefore are not to be used for active video. Additionally, the ITU specifies that the nominal range for video should be restricted to values between 16 and 235 for luma and between 16 and 240 for chroma.
ADV7184 Table 61.
ADV7184 0—The VS pin goes high at the middle of a line of video (even field). NEWAVMODE, New AV Mode, Address 0x31 [4] 0—EAV/SAV codes are generated to suit Analog Devices encoders. No adjustments are possible. 1 (default)—Enables the manual position of VS/FIELD and AV codes using Register 0x32, Register 0x33, and Register 0xE5 to Register 0xEA. Default register settings are CCIR 656 compliant; see Figure 27 for NTSC and Figure 32 for PAL.
ADV7184 FIELD 1 525 1 2 3 4 5 6 7 8 9 10 11 12 13 19 20 21 22 OUTPUT VIDEO H V NVBEG[4:0] = 0x5 NVEND[4:0] = 0x4 *BT.656-4 REG 0x04, BIT 7 = 1 F NFTOG[4:0] = 0x3 FIELD 2 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 283 284 285 OUTPUT VIDEO H V NVBEG[4:0] = 0x5 *BT.656-4 REG 0x04, BIT 7 = 1 NVEND[4:0] = 0x4 F 05479-027 NFTOG[4:0] = 0x3 *APPLIES IF NEMAVMODE = 0: MUST BE MANUALLY SHIFTED IF NEWAVMODE = 1. Figure 27. NTSC Default (ITU-R BT.
ADV7184 NVBEGSIGN ADVANCE BEGIN OF VSYNC BY NVBEG[4:0] 1 0 NVENDSIGN ADVANCE END OF VSYNC BY NVEND[4:0] DELAY BEGIN OF VSYNC BY NVBEG[4:0] 0 DELAY END OF VSYNC BY NVEND[4:0] NOT VALID FOR USER PROGRAMMING NOT VALID FOR USER PROGRAMMING ODD FIELD? ODD FIELD? NO YES NO NVBEGDELO NVBEGDELE NVENDDELO NVENDDELE 1 1 ADDITIONAL DELAY BY 1 LINE ADDITIONAL DELAY BY 1 LINE ADDITIONAL DELAY BY 1 LINE ADDITIONAL DELAY BY 1 LINE VSBHO VSBHE VSEHO VSEHE 1 1 ADVANCE BY 0.
ADV7184 For all NTSC/PAL vsync timing controls, both the V bit in the AV code and the vsync on the VS pin are modified. NFTOGDELO, NTSC Field Toggle Delay on Odd Field, Address 0xE7 [7] 0 (default)—No delay. NFTOGSIGN, NTSC Field Toggle Sign, Address 0xE7 [5] 0—Delays the field transition. Set for manual programming. 1 (default)—Advances the field transition. Not recommended for user programming.
ADV7184 FIELD 1 622 623 624 625 1 2 3 4 5 6 7 8 9 10 22 23 24 OUTPUT VIDEO H V PVBEG[4:0] = 0x5 PVEND[4:0] = 0x4 F PFTOG[4:0] = 0x3 FIELD 2 310 311 312 313 314 315 316 317 318 319 320 321 322 335 336 337 OUTPUT VIDEO H V PVBEG[4:0] = 0x5 PVEND[4:0] = 0x4 05479-032 F PFTOG[4:0] = 0x3 Figure 32. PAL Default (ITU-R BT.
ADV7184 PVBEGSIGN ADVANCE BEGIN OF VSYNC BY PVBEG[4:0] 0 1 DELAY BEGIN OF VSYNC BY PVBEG[4:0] PVENDSIGN ADVANCE END OF VSYNC BY PVEND[4:0] NOT VALID FOR USER PROGRAMMING 0 DELAY END OF VSYNC BY PVEND[4:0] NOT VALID FOR USER PROGRAMMING ODD FIELD? ODD FIELD? NO YES NO PVBEGDELO PVBEGDELE PVENDDELO PVENDDELE 1 1 ADDITIONAL DELAY BY 1 LINE ADDITIONAL DELAY BY 1 LINE ADDITIONAL DELAY BY 1 LINE ADDITIONAL DELAY BY 1 LINE VSBHO VSBHE VSEHO VSEHE 1 1 ADVANCE BY 0.5 LINE ADVANCE BY 0.
ADV7184 PFTOGSIGN, PAL Field Toggle Sign, Address 0xEA [5] ENVSPROC, Enable Vsync Processor, Address 0x01 [3] 0—Delays the field transition. Set for manual programming. This block provides extra filtering of the detected vsyncs to improve vertical lock. 1 (default)—Advances the field transition. Not recommended for user programming. 0—Disables the vsync processor. PFTOG, PAL Field Toggle, Address 0xEA [4:0] 1 (default)—Enables the vsync processor.
ADV7184 VDP Manual Configuration MAN_LINE_PGM, Enable Manual Line Programming of VBI Standards, Address 0x64 [7], User Sub Map different types of VBI standards decoded by VBI_DATA_Px_Ny are shown in Table 67. Note that the interpretation of its value depends on whether the ADV7184 is in PAL or NTSC mode. The user can configure the VDP to decode different standards on a line-to-line basis through manual line programming.
ADV7184 Table 67. VBI Data Standards for Manual Configuration VBI_DATA_Px_Ny 0000 0001 0010 0011 0100 0101 0110 0111 1000 to 1111 PAL—625/50 Disable VDP Teletext system identified by VDP_TTXT_TYPE VPS—ETSI EN 300 231 V 1.3.1 VITC WSS ITU-R BT.1119-1/ETSI.EN.300294 Reserved Reserved CC Reserved NTSC—525/60 Disable VDP Teletext system identified by VDP_TTXT_TYPE Reserved VITC CGMS EIA-J CPR-1204/IEC 61880 Gemstar 1× Gemstar 2× CC EIA-608 Reserved Table 68.
ADV7184 VDP_TTXT_TYPE_MAN_ENABLE, Enable Manual Selection of Teletext Type, Address 0x60 [2], User Sub Map ADF_DID [4:0], User-Specified Data ID Word in Ancillary Data, Address 0x62 [4:0], User Sub Map 0 (default)—Manual programming of the teletext type is disabled. These bits select the DID to be inserted into the ancillary data stream with the data decoded by the VDP. 1—Manual programming of the teletext type is enabled. The default value of ADF_DID [4:0] is 10101.
ADV7184 The checksum value of B8 to B0 is equal to the nine LSBs of the sum of the nine LSBs of the DID, SDID, and dc, as well as all UDWs in the packet. Prior to the start of the checksum count cycle, all checksum and carry bits are preset to 0. Any carry resulting from the checksum count cycle is ignored. numbering system of ITU-R BT.470, ranging from 1 to 625 in a 625-line system and from 1 to 263 in a 525-line system.
ADV7184 Table 72. Ancillary Data in Byte Output Format 1 Byte 0 1 2 3 B9 0 1 1 EP B8 0 1 1 EP 4 EP EP 5 EP EP 0 6 EP EP padding [1:0] 7 EP EP 0 8 EP EP Even_Field 9 EP EP 0 10 11 12 13 14 . . . n−3 n−2 n−1 1 . . . 1 1 B8 . . . 0 0 B7 0 1 1 0 B6 0 1 1 B5 0 1 1 B4 B3 0 0 1 1 1 1 I2C_DID6_2 [4:0] B2 0 1 1 B1 0 1 1 0 B0 0 1 1 0 0 0 SDID. 0 0 Data count. 0 0 ID0 (User Data-Word 1). Line_number [9:5] 0 0 ID1 (User Data-Word 2).
ADV7184 Table 74.
ADV7184 I2C INTERFACE VDP—Content-Based Data Update 2 Dedicated I C readback registers are available for CC, CGMS, WSS, Gemstar, VPS, PDC/UTC, and VITC. Because teletext is a high data rate standard, data extraction is supported only through the ancillary data packet. The details of these registers and their access procedures are described in this section. User Interface for I2C Readback Registers The VDP decodes all enabled VBI data standards in real time.
ADV7184 VDP—Interrupt-Based Reading of VDP I2C Registers Some VDP status bits are also linked to the interrupt request controller so that the user does not have to poll the AVAILABLE status bit. The user can configure the video decoder to trigger an interrupt request on the INT pin in response to the valid data available in I2C registers. This function is available for the following data types: • • CGMS or WSS.
ADV7184 STDI_DVALID, Standard Identification Data Valid Read Back, Address 0xB1 [7] VDP_CGMS_WSS_CHNGD_CLR, Address 0x4F [2], User Sub Map VDP_VITC_CLR, Address 0x4F [6], User Sub Map X—This bit is set by the ADV7184 as soon as the measurements of the STDI block are finished. A high level signals the validity of the BL, LCVS, LCF, and STDI_INTLCD parameters. To prevent false readouts, especially during the signal acquisition, the DVALID bit only goes high after recording four fields with the same length.
ADV7184 ENABLE STDI FUNCTION STDI_LINE_COUNT_MODE = 1 STDI Readback Values for SD, PR, and HD The readback values provided are only valid when using a crystal with the recommended 28.63636 MHz frequency. MONITORS IN-LOCK STAUS Table 76.
ADV7184 I2C READBACK REGISTERS WST_PKT_DECOD_DISABLE, Disable Hamming Decoding of Bytes in WST, Address 0x60 [3], User Sub Map Teletext Because teletext is a high data rate standard, the decoded bytes are available only as ancillary data. However, a TTXT_AVL bit is provided in I2C so that the user can check whether the VDP has detected teletext. Note that the TTXT_AVL bit is a plain status bit and does not use the protocol identified in the I2C Interface section.
ADV7184 CGMS and WSS CC The CGMS and WSS data packets convey the same type of information for different video standards. WSS is for PAL and CGMS is for NTSC; therefore, the CGMS and WSS readback registers are shared. WSS is biphase coded, and the VDP performs a biphase decoding to produce the 14 raw WSS bits in the CGMS/ WSS readback I2C registers and to set the CGMS_WSS_AVL bit. Two bytes of decoded closed caption data are available in the I2C registers.
ADV7184 VDP_CGMS_WSS_ DATA_1[5:0] VDP_CGMS_WSS_DATA_2 0 RUN-IN SEQUENCE 1 2 3 4 5 6 7 0 1 2 3 4 5 START CODE ACTIVE VIDEO 11.0µs 05479-037 38.4µs 42.5µs Figure 39. WSS Waveform +100 IRE REF +70 IRE VDP_CGMS_WSS_DATA_2 0 1 2 3 4 5 6 VDP_CGMS_WSS_ DATA_0[3:0] VDP_CGMS_WSS_DATA_1 7 0 1 2 3 4 5 6 7 0 1 2 3 0 IRE 49.1µs ± 0.5µs 11.2µs 05479-038 –40 IRE CRC SEQUENCE 2.235µs ± 20ns Figure 40. CGMS Waveform 10.5 ± 0.25µs 12.91µs SEVEN CYCLES OF 0.
ADV7184 VITC_CLEAR, VITC Clear, Address 0x78 [6], User Sub Map, Write Only, Self-Clearing VITC VITC has a sequence of 10 syncs in between each data byte. The VDP strips these syncs from the data stream to output only the data bytes. The VITC results are available in the VDP_VITC_DATA_0 to VDP_VITC_DATA_8 registers (Register 0x92 to Register 0x9A, user sub map). 1—Reinitializes the VITC readback registers. VITC_AVL, VITC Available, Address 0x78 [6], User Sub Map, Read Only 0—VITC data was not detected.
ADV7184 VPS/PDC/UTC/Gemstar VPS The readback registers for VPS, PDC, and UTC are shared. Gemstar is a high data rate standard and therefore is available only through the ancillary stream. For evaluation purposes, any one line of Gemstar is available through the I2C registers sharing the same register space as PDC, UTC, and VPS. Therefore, only one of the following standards can be read through the I2C at a time: VPS, PDC, UTC, or Gemstar. The VPS data bits are biphase decoded by the VDP.
ADV7184 Table 83.
ADV7184 The format of the data packet depends on the following criteria: Entries within the packet are as follows: • Transmission is Gemstar 1× or Gemstar 2×. • A fixed preamble sequence of 0x00, 0xFF, and 0xFF. • Data is output in 8-bit or 4-bit format (see the GDECAD, Gemstar Decode Ancillary Data Format, Address 0x4C [0] section). • The data identification word (DID) (10-bit value), the value of which is 0x140 for a Gemstar or CC data packet.
ADV7184 Table 85. Data Byte Allocation Gemstar 2× 1 1 0 0 Raw Information Bytes Retrieved from the Video Line 4 4 2 2 GDECAD 0 1 0 1 Gemstar Bit Names • DID. The data identification value is 0x140 (10-bit value). Care has been taken that in 8-bit systems, the two LSBs do not carry vital information. • EP and EP. The EP bit is set to ensure even parity on the data-word D [8:0]. Even parity means there is always an even number of 1s within the D [8:0] bit arrangement. This includes the EP bit.
ADV7184 Table 86.
ADV7184 Table 89.
ADV7184 Table 92.
ADV7184 To retrieve closed caption data services on PAL (Line 335), GDECEL [14] must be set. Table 95. PAL Line Enable Bits and Corresponding Line Numbering1 The default value of GDECEL [15:0] is 0x0000. This setting instructs the decoder not to attempt to decode Gemstar or CC data from any line in the even field. The user should only enable Gemstar slicing on lines where VBI data is expected. Line [3:0] 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 Table 94.
ADV7184 GDECOL [15:0], Gemstar Decoding Odd Lines, Address 0x4A [7:0], Address 0x4B [7:0] The 16 bits of the GDECOL [15:0] form a collection of 16 individual line decode enable signals. See Table 94 and Table 95. To retrieve closed caption data services on NTSC (Line 21), GDECOL [11] must be set. The active video content (luminance magnitude) over a line of video is summed together.
ADV7184 LB_TH [4:0], Letterbox Threshold Control, Address 0xDC [4:0] 6 Table 97.
ADV7184 Interrupt Request Output Operation INTRQ_OP_SEL [1:0], Interrupt Duration Select, Address 0x40 [1:0], User Sub Map When an interrupt event occurs, the interrupt pin INTRQ goes low, with a programmable duration given by INTRQ_DUR_SEL [1:0] Table 99. INTRQ_OP_SEL [1:0] Function INTRQ_OP_SEL [1:0] 00 (default) 01 10 11 INTRQ_DUR_SEL [1:0], Interrupt Duration Select, Address 0x40 [7:6], User Sub Map Table 98.
ADV7184 PIXEL PORT CONFIGURATION The ADV7184 has a very flexible pixel port that can be configured in a variety of formats to accommodate downstream ICs. Table 101 and Table 102 summarize the various functions that the ADV7184 pins can have in different modes of operation. SWPC, Swap Pixel Cr/Cb, Address 0x27 [7] The order of components, for example, the order of Cr and Cb, on the output pixel bus can be changed. Refer to the SWPC, Swap Pixel Cr/Cb, Address 0x27 [7] section.
ADV7184 MPU PORT DESCRIPTION The ADV7184 supports a 2-wire (I2C-compatible) serial interface. Two inputs, serial data (SDA) and serial clock (SCLK), carry information between the ADV7184 and the system I2C master controller. Each slave device is recognized by a unique address. The ADV7184 I2C port allows the user to set up and configure the decoder and then to read back captured VBI data.
ADV7184 REGISTER ACCESSES I2C SEQUENCER The MPU can write to and read from all of the ADV7184 registers except those that are read only or write only. The subaddress register determines which register the next read or write operation accesses. All communications with the part through the bus start with an access to the subaddress register. A read/write operation is then performed from/to the target address, which then increments to the next address until a stop command on the bus is performed.
ADV7184 I2C REGISTER MAPS USER MAP The collective name for the registers in Table 104 is the user map. Table 104. User Map Register Details Address Dec Hex 0 00 1 01 3 03 4 04 RW RW RW RW RW 7 VID_SEL.3 7 8 10 11 12 RW RW RW RW RW AD_SEC525_EN CON.7 BRI.7 HUE.7 DEF_Y.
ADV7184 Address Dec Hex 72 48 73 49 74 4A 75 4B 76 4C 77 4D 78 4E 80 50 81 51 105 69 134 86 143 8F 153 154 155 156 157 177 178 179 180 195 196 202 203 220 221 222 223 225 226 227 228 229 230 231 232 233 234 235 236 237 237 238 99 9A 9B 9C 9D B1 B2 B3 B4 C3 C4 CA CB DC DD DE DF E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED ED EE Register Name Gemstar Control 1 Gemstar Control 2 Gemstar Control 3 Gemstar Control 4 Gemstar Control 5 CTI DNR Control 1 CTI DNR Control 2 CTI DNR Control 4 Lock Count Config 1 STDI Cont
ADV7184 Table 105 provides a detailed description of the registers located in the user map. Table 105. User Map Detailed Description Address 0x00 Register Input Control Bit Description INSEL [3:0]. These bits allow the user to select an input channel and format. VID_SEL [3:0]. These bits allow the user to select the input video standard. 0x01 Video Selection Reserved. ENVSPROC. Reserved. BETACAM. Enable BETACAM levels. This bit sets the target value for AGC operation. ENHSPLL. Reserved.
ADV7184 Address 0x03 0x04 Register Output Control Extended Output Control 0x07 Autodetect Enable 0x08 Contrast Register 0x09 Reserved Bit 1 Bit Description 7 6 5 4 3 2 1 0 Comments SD_DUP_AV. This bit duplicates the AV codes 0 AV codes to suit 8-bit interleaved from the luma into the chroma path. data output 1 AV codes duplicated for 16-bit interfaces Reserved. 0 Set as default OF_SEL [3:0]. These bits allow the user to 0 0 0 0 Reserved choose from a set of output formats.
ADV7184 Bit 1 7 6 5 4 3 2 1 0 Comments 0 0 0 0 0 0 0 0 Address 0x0A Register Brightness Register Bit Description BRI [7:0]. These bits control the brightness of the video signal. 0x0B Hue Register 0x0C Default Value Y HUE [7:0]. These bits contain the value for the 0 0 0 0 0 0 0 0 color hue adjustment. DEF_VAL_EN. Default value enable. 0 Free-run mode dependent on DEF_VAL_AUTO_EN 1 Force free-run mode on and output blue screen DEF_VAL_AUTO_EN. Default value.
ADV7184 Address Register Analog Control Internal (Write Only) 0x14 Analog Clamp Control 0x15 Digital Clamp Control 1 Bit Description FREE_RUN_ACT. STD_FLD_LEN. INTERLACED. PAL_SW_LOCK. Reserved. XTAL_TTL_SEL. Reserved. Reserved. CCLEN. Current clamp enable. This bit allows the user to switch off the current sources in the analog front end. Reserved. Reserved. DCFE. Digital clamp freeze enable.
ADV7184 Address Register Bit Description CSFM [2:0]. C-shaping filter mode. These bits allow selection from a range of lowpass chrominance filters, SH1to SH5, and wideband mode. Bit 1 7 6 5 4 3 2 1 0 Comments 0 0 0 Automatic selection of 15 MHz 0 0 1 Automatic selection of 2.17 MHz 0 0 1 1 1 1 0x18 Shaping Filter Control 2 1 1 0 0 1 1 0 1 0 1 0 1 WYSFM [4:0]. Wideband Y-shaping filter mode.
ADV7184 Address Register Bit Description CTA [2:0]. Chroma timing adjust. These bits allow a specified timing difference between the luma and chroma samples. AUTO_PDC_EN. This bit automatically programs the LTA/CTA values to align luma and chroma at the output for all modes of operation. SWPC. This bit allows the Cr and Cb samples to be swapped. 0x2B Miscellaneous Gain Control 7 6 5 0 0 0 0 1 1 1 1 0 1 0 1 PW_UPD. Peak white update. This bit determines the rate of gain change. Reserved. CKE.
ADV7184 Address 0x31 Register Vsync Field Control 1 0x32 Vsync Field Control 2 0x33 Vsync Field Control 3 0x34 Hsync Position Control 1 0x35 Hsync Position Control 2 0x36 Hsync Position Control 3 Polarity 0x37 Bit 1 Bit Description 7 6 5 4 3 2 1 0 Comments Reserved. 0 1 0 Set to default HVSTIM. This bit selects where within a line of 0 Start of line relative to HSE video the VS signal is asserted. 1 Start of line relative to HSB NEWAVMODE. Sets the EAV/SAV mode.
ADV7184 Address Register Bit Description CCMN [2:0]. Chroma comb mode NTSC. CTAPSN [1:0]. Chroma comb taps NTSC. 0x39 PAL Comb Control YCMP [2:0]. Luma comb mode PAL. CCMP [2:0]. Chroma comb mode PAL. CTAPSP [1:0]. Chroma comb taps PAL. 0x3A ADC Control PWRDN_ADC_3. This bit enables powerdown of ADC3. PWRDN_ADC_2. This bit enables powerdown of ADC2. PWRDN_ADC_1. This bit enables powerdown of ADC1. PWRDN_ADC_0. This bit enables powerdown of ADC0. 0x3D Manual Window Control Reserved. Reserved.
ADV7184 Address 0x41 Register Resample Control Bit Description Reserved. SFL_INV. This bit controls the behavior of the PAL switch bit. 0x48 0x49 Gemstar Control 1 Gemstar Control 2 Reserved. GDECEL [15:8]. See the Comments column. GDECEL [7:0]. See the Comments column. 0x4A Gemstar Control 3 GDECOL [15:8]. See the Comments column. 0x4B Gemstar Control 4 GDECOL [7:0]. See the Comments column. 0x4C Gemstar Control 5 0x4D CTI DNR Control 1 GDECAD.
ADV7184 Address 0x69 Register Configuration 1 0x86 STDI Control 0x8F Free-Run Line Length 1 0x99 CCAP1 (Read Only) 0x9A CCAP2 (Read Only) 0x9B Letterbox 1 (Read Only) Letterbox 2 (Read Only) 0x9C 0x9D Letterbox 3 (Read Only) 0xB1 Standard Ident 1 (Read Only) 0xB2 Standard Ident 2 (Read Only) 0xB3 Standard Ident 3 (Read Only) 0xB4 Standard Ident 4 (Read Only) ADC Switch 1 0xC3 Bit Description SDM_SEL [1:0]. Y/C and CVBS autodetect mode select.
ADV7184 Address Register Bit Description ADC1_SW [3:0]. Manual muxing control for ADC1. 0xC4 ADC Switch 2 ADC2_SW [3:0]. Manual muxing control for ADC2. Reserved. ADC_SW_MAN_EN. This bit enables manual setting of the input signal muxing. 0xCA Field Length Count 1 (Read Only) 0xCB 0xDC Field Length Count 2 (Read Only) Letterbox Control 1 0xDD Letterbox Control 2 FCL [12:8]. The number of 27 MHz clock cycles between successive vsyncs. Reserved. FCL[7:0]. See FCL [12:8]. LB_TH [4:0].
ADV7184 Address 0xE4 Register SD Saturation Cr 0xE5 NTSC V Bit Begin 0xE6 NTSC V Bit End 0xE7 NTSC F Bit Toggle 0xE8 PAL V Bit Begin 0xE9 PAL V Bit End 0xEA PAL F Bit Toggle Bit Description SD_SAT_CR [7:0]. These bits adjust the saturation of the picture by affecting gain on the Cr channel. NVBEG [4:0]. Number of lines after lCOUNT rollover to set V high. NVBEGSIGN. Bit 1 7 6 5 4 3 2 1 0 Comments 1 0 0 0 0 0 0 0 Chroma gain = 0 dB 0 0 1 0 1 NTSC default (ITU-R BT.
ADV7184 Address 0xEB Register V Blank Control 1 Bit Description PVBIELCM [1:0]. PAL VBI even field luma comb mode. PVBIOLCM [1:0]. PAL VBI odd field luma comb mode. NVBIELCM [1:0]. NTSC VBI even field luma comb mode. NVBIOLCM [1:0]. NTSC VBI odd field luma comb mode. 0xEC V Blank Control 2 PVBIECCM [1:0]. PAL VBI even field chroma comb mode. Bit 1 7 6 5 4 3 2 1 0 0 1 1 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 PVBIOCCM [1:0]. PAL VBI odd field chroma comb mode.
ADV7184 Address 0xEE 0xEF Register FB_CONTROL 2 FB_CONTROL 3 Bit 1 Bit Description 7 6 5 4 3 2 1 0 Comments MAN_ALPHA_VAL [6:0]. These bits determine 0 0 0 0 0 0 0 in what proportion the video from the CVBS and RGB sources are blended. FB_CSC_MAN. 0 Automatic configuration of the CSC for SCART support 1 Enable manual programming of CSC FB_EDGE_SHAPE [2:0]. 0 0 0 No edge shaping 0 0 1 Level 1 edge shaping CNTR_ENABLE. FB_SP_ADJUST. 0xF0 FB_CONTROL 4 FB_DELAY [3:0]. 0xF1 FB_CONTROL 5 Reserved.
ADV7184 Address Register Bit Description ADC3_SW [3:0]. 0xF4 Drive Strength DR_STR_S [1:0]. These bits select the drive strength for the sync output signals. 7 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 6 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 5 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 DR_STR_C [1:0]. These bits select the drive strength for the clock output signal. 0 0 1 1 DR_STR [1:0]. These bits select the drive strength for the data output signals. Can be increased or decreased for EMC or crosstalk reasons.
ADV7184 USER SUB MAP The collective name for the subaddress registers in Table 106 is user sub map. To access the user sub map, SUB_USR_EN in Register Address 0x0E (user map) must be programmed to 1. Table 106. User Sub Map Register Details Address 3 2 1 0 Reset Value INTRQ_OP_SEL.0 0001x000 10 SD_LOCK_Q – Dec Hex Register Name RW 7 6 5 4 64 40 Interrupt Configuration 0 RW INTRQ_DUR_ SEL.1 INTRQ_DUR_ SEL.0 MV_INTRQ_ SEL.1 MV_INTRQ_ SEL.
ADV7184 Address Reset Value Dec Hex Register Name RW 7 6 5 4 3 2 1 0 116 74 VDP_LINE_01E RW VBI_DATA_ P21_N19.3 VBI_DATA_P21_ N19.2 VBI_DATA_P21_ N19.1 VBI_DATA_P21_ N19.0 VBI_DATA_P334_ N282.3 VBI_DATA_P334_ N282.2 VBI_DATA_P334_ N282.1 VBI_DATA_ P334_N282.0 00000000 00 117 75 VDP_LINE_01F RW VBI_DATA_ P22_N20.3 VBI_DATA_P22_ N20.2 VBI_DATA_P22_ N20.1 VBI_DATA_P22_ N20.0 VBI_DATA_P335_ N283.3 VBI_DATA_P335_ N283.2 VBI_DATA_P335_ N283.1 VBI_DATA_ P335_N283.
ADV7184 Table 107 provides a detailed description of the registers located in the user sub map. Table 107. User Sub Map Detailed Description Address Register 0x40 Interrupt Configuration 0 Bit Description INTRQ_OP_SEL [1:0]. Interrupt drive level select. MPU_STIM_INTRQ. Manual interrupt set mode. Reserved. MV_INTRQ_SEL [1:0]. Macrovision interrupt select. INTRQ_DUR_SEL [1:0]. Interrupt duration select.
ADV7184 Address Register 0x45 Raw Status 2 (Read Only) Bit 1 7 6 5 4 3 2 1 0 0 1 x x x 0 1 x x 0 1 0 Bit Description CCAPD. Reserved. EVEN_FIELD. Reserved. MPU_STIM_INTRQ. 0x46 Interrupt Status 2 (Read Only) CCAPD_Q. 1 GEMD_Q. 0 1 Reserved. SD_FIELD_CHNGD_Q. Reserved. Reserved. MPU_STIM_INTRQ_Q. Interrupt Clear 2 (Write Only) x x 0 1 CCAPD_CLR. 0 1 GEMD_CLR. 0 1 Reserved. SD_FIELD_CHNGD_CLR. Interrupt Mask 2 (Read/Write) x x 0 1 CCAPD_MSKB. 0 1 GEMD_MSKB. 0 1 CGMS_MSKB.
ADV7184 Address Register 0x4A Interrupt Status 3 (Read Only) Bit Description SD_OP_CHNG_Q. This bit indicates if the SD 60 Hz or SD 50 Hz frame rate is at output. Bit 1 7 6 5 4 3 2 1 0 0 1 0 SD_V_LOCK_CHNG_Q. 1 SD_H_LOCK_CHNG_Q. 0 1 SD_AD_CHNG_Q. SD autodetect changed. 0 1 SCM_LOCK_CHNG_Q. SECAM lock. 0 1 0 PAL_SW_LK_CHNG_Q. 1 0x4B Interrupt Clear 3 (Write Only) Reserved. Reserved. SD_OP_CHNG_CLR. x x 0 1 SD_V_LOCK_CHNG_CLR. 0 1 SD_H_LOCK_CHNG_CLR. 0 1 SD_AD_CHNG_CLR.
ADV7184 Address Register 0x4F Interrupt Clear 4 (Write Only) Bit 1 Bit Description 7 6 5 4 3 2 1 0 0 VDP_GS_VPS_PDC_UTC_CHNG_Q. See Register 0x9C, Bit 5, of the user sub map to determine whether an interrupt is issued for 1 a change in detected data or when data is detected regardless of content. Reserved. x 0 VDP_VITC_Q. 1 Reserved. x VDP_CCAPD_CLR. 0 1 Reserved. x VDP_CGMS_WSS_CHNGD_CLR. 0 1 Reserved. x VDP_GS_VPS_PDC_UTC_CHNG_CLR. 0 1 Reserved. VDP_VITC_CLR. 0x50 Interrupt Mask 4 Reserved.
ADV7184 Address Register 0x62 VDP_ADF_Config_1 Bit Description ADF_DID [4:0]. Bit 1 7 6 5 4 3 2 1 0 1 0 1 0 1 0 0 0 1 1 0 ADF_MODE [1:0]. 1 1 ADF_ENABLE. 0 1 0x63 VDP_ADF_Config_2 ADF_SDID [5:0]. Reserved. DUPLICATE_ADF. 1 0 1 0 1 0 VDP_LINE_00E VBI_DATA_P318 [3:0]. Reserved. MAN_LINE_PGM.
ADV7184 Address Register 0x6F VDP_LINE_019 0x70 VDP_LINE_01A Bit Description VBI_DATA_P329_N277 [3:0]. Bit 1 7 6 5 4 3 2 1 0 0 0 0 0 VBI_DATA_P16_N14 [3:0]. 0 0 0 0 VBI_DATA_P330_N278 [3:0]. VBI_DATA_P17_N15 [3:0]. 0x71 VDP_LINE_01B VDP_LINE_01C VDP_LINE_01D VDP_LINE_01E VDP_LINE_01F VDP_LINE_020 VDP_LINE_021 VDP_STATUS (Read Only) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VBI_DATA_P337_N285 [3:0]. VBI_DATA_P24_N22 [3:0]. 0x78 0 0 0 0 VBI_DATA_P336_N284 [3:0].
ADV7184 Address Register Bit Description GS_PDC_VPS_UTC_CLEAR. Bit 1 7 6 5 4 3 2 1 0 0 1 Reserved. VITC_CLEAR. 0x79 0x7A 0x7D 0x7E 0x7F 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F 0x90 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B VDP_CCAP_DATA_0 (Read Only) VDP_CCAP_DATA_1 (Read Only) VDP_CGMS_WSS_DATA_0 (Read Only) Comments Does not reinitialize the GS/PDC/VPS/UTC registers. Refreshes the GS/PDC/VPS/UTC readback registers. Notes This is a self-clearing bit.
ADV7184 Address Register 0x9C VDP_OUTPUT_SEL Bit Description Reserved. WSS_CGMS_CB_CHANGE. Bit 1 7 6 5 4 3 2 1 0 0 0 0 0 0 1 GS_VPS_PDC_UTC_CB_CHANGE. 0 1 I2C_GS_VPS_PDC_UTC [1:0]. 1 0 0 1 1 0 1 0 1 Shading indicates default settings. Rev. A | Page 108 of 112 Comments Notes Disable content-based updating of CGMS and WSS data. Enable content-based updating of CGMS and WSS data. Disable content-based updating of Gemstar, VPS, PDC, and UTC data.
ADV7184 PCB LAYOUT RECOMMENDATIONS ANALOG INTERFACE INPUTS Care should be taken when routing the inputs on the PCB. Track lengths should be kept to a minimum, and 75 Ω trace impedances should be used when possible. Trace impedances other than 75 Ω increase the chance of reflections. POWER SUPPLY DECOUPLING It is recommended to decouple each power supply pin with 0.1 μF and 10 nF capacitors. The fundamental idea is to have a decoupling capacitor within about 0.5 cm of each power pin.
ADV7184 DIGITAL INPUTS Use the following guidelines to ensure correct operation: The digital inputs on the ADV7184 are designed to work with 3.3 V signals and are not tolerant of 5 V signals. Extra components are needed if 5 V logic signals are required to be applied to the decoder. • Use a crystal of the correct frequency, 28.63636 MHz. Tolerance should be 50 ppm or better. • User a parallel-resonant crystal. XTAL AND LOAD CAPACITOR VALUES SELECTION • Know the Cload for the crystal part selected.
ADV7184 TYPICAL CIRCUIT CONNECTION An example of how to connect the ADV7184 video decoder is shown in Figure 52. For a detailed schematic diagram for the ADV7184, refer to the ADV7184 evaluation note, which can be obtained from an Analog Devices representative. FERRITE BEAD DVDDIO (3.3V) 33µF PVDD (1.8V) 33µF AVDD (3.3V) AGND 10µF 0.1µF AGND AGND FERRITE BEAD 33µF AGND 10µF 0.
ADV7184 OUTLINE DIMENSIONS 0.75 0.60 0.45 16.20 16.00 SQ 15.80 1.60 MAX 61 80 60 1 PIN 1 14.20 14.00 SQ 13.80 TOP VIEW (PINS DOWN) 1.45 1.40 1.35 0.15 0.05 0.20 0.09 7° 3.5° 0° 0.10 MAX COPLANARITY SEATING PLANE VIEW A ROTATED 90° CCW 20 41 40 21 VIEW A 0.65 BSC LEAD PITCH 0.38 0.32 0.22 COMPLIANT TO JEDEC STANDARDS MS-026-BEC Figure 53.