Multiformat SDTV Video Decoder ADV7189B FEATURES Multiformat video decoder supports NTSC-(J, M, 4.
ADV7189B TABLE OF CONTENTS Introduction ...................................................................................... 4 General Setup.............................................................................. 21 Analog Front End ......................................................................... 4 SD Color Controls...................................................................... 23 Standard Definition Processor ...................................................
ADV7189B Crystal Load Capacitor Value Selection...................................98 62H 128H Typical Circuit Connection ...........................................................99 63H 129H Outline Dimensions......................................................................101 64H 130H Ordering Guide .........................................................................101 65H 13H REVISION HISTORY 9/05—Rev. A to Rev. B Changes to Table 1 .....................................................
ADV7189B INTRODUCTION The ADV7189B is a high quality, single chip, multiformat video decoder that automatically detects and converts PAL, NTSC, and SECAM standards in the form of composite, S-Video, and component video into a digital ITU-R BT.656 format. The advanced and highly flexible digital output interface enables performance video decoding and conversion in line-locked, clock-based systems.
04983-0-001 12 INPUT MUX SCLK SDA ALSB CVBS S-VIDEO YPrPb AIN1–AIN12 A/D CLAMP 12 12 12 SERIAL INTERFACE CONTROL AND VBI DATA SYNC PROCESSING AND CLOCK GENERATION A/D A/D CLAMP CLAMP Figure 1. Rev.
ADV7189B SPECIFICATIONS ELECTRICAL CHARACTERISTICS At AVDD = 3.15 V to 3.45 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.65 V to 2.0 V, operating temperature range, unless otherwise specified. Table 1. Parameter 1, 2 STATIC PERFORMANCE Resolution (Each ADC) Integral Nonlinearity Differential Nonlinearity DIGITAL INPUTS Input High Voltage Input Low Voltage Input Current 3 0F 1F Symbol Test Conditions N INL DNL BSL at 54 MHz BSL at 54 MHz VIH VIL IIN 2F 3F Typ Max Unit –1.5/+2.
ADV7189B VIDEO SPECIFICATIONS Guaranteed by characterization. At AVDD = 3.15 V to 3.45 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.65 V to 2.0 V; operating temperature range, unless otherwise specified. Table 2.
ADV7189B TIMING SPECIFICATIONS Guaranteed by characterization. AVDD = 3.15 V to 3.45 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.65 V to 2.0 V; operating temperature range, unless otherwise specified. Table 3.
ADV7189B THERMAL SPECIFICATIONS Table 5. Parameter 1, 2 THERMAL CHARACTERISTICS Junction-to-Case Thermal Resistance Junction-to-Ambient Thermal Resistance (Still Air) 6F 1 2 7F Symbol Test Conditions Min θJC θJA 4-layer PCB with solid ground plane 4-layer PCB with solid ground plane 7.6 38.1 Temperature range: TMIN to TMAX, –40°C to +85°C. (0°C to 70°C for ADV7189BKSTZ) The min/max specifications are guaranteed over this range. TIMING DIAGRAMS t3 t5 t3 SDA t4 t7 t2 t8 Figure 2.
ADV7189B ABSOLUTE MAXIMUM RATINGS Table 6. Parameter AVDD to GND AVDD to AGND DVDD to DGND PVDD to AGND DVDDIO to DGND DVDDIO to AVDD PVDD to DVDD DVDDIO – PVDD DVDDIO – DVDD AVDD – PVDD AVDD – DVDD Digital Inputs Voltage to DGND Digital Output Voltage to DGND Analog Inputs to AGND Maximum Junction Temperature (TJ Max) Storage Temperature Range Infrared Reflow Soldering (20 sec) Rating 4V 4V 2.2 V 2.2 V 4V –0.3 V to +0.3 V –0.3 V to +0.3 V –0.3 V to +2 V –0.3 V to +2 V –0.3 V to +2 V –0.3 V to +2 V –0.
ADV7189B FIELD OE NC NC P16 P17 P18 P19 DVDD DGND NC NC SCLK SDA ALSB NC RESET NC AIN6 AIN12 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 VS 1 60 AIN5 HS 2 59 AIN11 DGND 3 58 AIN4 DVDDIO 4 57 AIN10 P15 5 56 AGND P14 6 55 CAPC2 P13 7 54 CAPC1 P12 8 53 AGND DGND 9 52 CML ADV7189B DVDD 10 51 REFOUT TOP VIEW (Not to Scale) INTRQ 11 50 AVDD SFL 12 49 CAPY2 NC 13 48 CAPY1 DGND 14 47 AGN
ADV7189B Table 7. Pin Function Descriptions Pin No. 3, 9, 14, 31, 71 39, 40, 47, 53, 56 4, 15 10, 30, 72 50 38 42, 44, 46, 58, 60, 62, 41, 43, 45, 57, 59, 61 11 Mnemonic DGND AGND Type G G Function Digital Ground. Analog Ground. DVDDIO DVDD AVDD PVDD AIN1toAIN12 P P P P I Digital I/O Supply Voltage (3.3 V). Digital Core Supply Voltage (1.8 V). Analog Supply Voltage (3.3 V). PLL Supply Voltage (1.8 V). Analog Video Input Channels. INTRQ O Interrupt Request Output.
ADV7189B ANALOG FRONT END ANALOG INPUT MUXING INSEL[3:0] INTERNAL MAPPING FUNCTIONS AIN1 AIN7 AIN2 AIN8 AIN3 AIN9 AIN4 AIN10 AIN5 AIN11 AIN6 AIN12 1 ADC0_SW[3:0] 0 ADC0 AIN3 AIN9 AIN4 AIN10 AIN5 AIN11 AIN6 AIN12 1 ADC1_SW[3:0] 0 ADC1 AIN2 AIN8 AIN5 AIN11 AIN6 AIN12 1 ADC2_SW[3:0] 0 ADC2 04983-0-006 AIN1 AIN7 AIN2 AIN8 AIN3 AIN9 AIN4 AIN10 AIN5 AIN11 AIN6 AIN12 ADC_SW_MAN_EN Figure 6.
ADV7189B CONNECTING ANALOG SIGNALS TO ADV7189 ADI-RECOMMENDED INPUT MUXING; SEE TABLE 9 SET INSEL[3:0] FOR REQUIRED MUXING CONFIGURATION NO SET INSEL[3:0] TO CONFIGURE ADV7189B TO DECODE VIDEO FORMAT: CVBS: 0000 YC: 0110 YPrPb: 1001 USE MANUAL INPUT MUXING (ADC_SW_MAN_EN, ADC0_SW, ADC1_SW, ADC2_SW) 04983-0-007 YES Figure 7. Input Muxing Overview Table 8.
ADV7189B This means INSEL must be used to tell the ADV7189B whether the input signal is of component, YC, or CVBS format. Manual Input Muxing By accessing a set of manual override muxing registers, the analog input muxes of the ADV7189B can be controlled directly. This is referred to as manual input muxing. Manual input muxing overrides other input muxing control bits, for example, INSEL. The manual muxing is activated by setting the ADC_SW_MAN_EN bit.
ADV7189B GLOBAL CONTROL REGISTERS Register control bits listed in this section affect the whole chip. PWRDN_ADC_0, Address 0x3A[3] POWER-SAVE MODES When PWRDN_ADC_0 is 0 (default), the ADC is in normal operation. Power-Down PDBP, Address 0x0F[2] When PWRDN_ADC_0 is 1, ADC 0 is powered down. The digital core of the ADV7189B can be shut down by using a pin (PWRDN) and a bit (PWRDN, see below). The PDBP controls which of the two has the higher priority. The default is to give the pin (PWRDN) priority.
ADV7189B Individual drive strength controls are provided via the DR_STR_XX bits. GLOBAL PIN CONTROL Three-State Output Drivers TOD, Address 0x03[6] This bit allows the user to three-state the output drivers of the ADV7189B. Upon setting the TOD bit, the P[19:0], HS, VS, FIELD, and SFL pins are three-stated. The timing pins (HS/VS/FIELD) can be forced active via the TIM_OE bit. For more information on three-state control, refer to the Three-State LLC Drivers and the Timing Signals Output Enable sections.
ADV7189B Enable Subcarrier Frequency Lock Pin EN_SFL_PIN Address 0x04[1] Polarity LLC Pin PCLK Address 0x37[0] The EN_SFL_PIN bit enables the output of subcarrier lock information (also known as GenLock) from the ADV7189B core to an encoder in a decoder-encoder back-to-back arrangement. The polarity of the clock that leaves the ADV7189B via the LLC1 and LLC2 pins can be inverted using the PCLK bit. When EN_SFL_PIN is 0 (default), the subcarrier frequency lock output is disabled.
ADV7189B GLOBAL STATUS REGISTERS Four registers provide summary information about the video decoder. The IDENT register allows the user to identify the revision code of the ADV7189B. The other three registers contain status bits from the ADV7189B. Table 15. STATUS 1 Function STATUS 1[7:0] 0 1 Bit Name IN_LOCK LOST_LOCK IDENTIFICATION 2 3 FSC_LOCK FOLLOW_PW 4 5 6 7 AD_RESULT.0 AD_RESULT.1 AD_RESULT.
ADV7189B STANDARD DEFINITION PROCESSOR (SDP) STANDARD DEFINITION PROCESSOR MACROVISION DETECTION DIGITIZED CVBS DIGITIZED Y (YC) DIGITIZED CVBS DIGITIZED C (YC) VBI DATA RECOVERY LUMA DIGITAL FINE CLAMP CHROMA DIGITAL FINE CLAMP CHROMA DEMOD STANDARD AUTODETECTION SLLC CONTROL LUMA FILTER GAIN CONTROL LUMA RESAMPLE SYNC EXTRACT LINE LENGTH PREDICTOR RESAMPLE CONTROL CHROMA FILTER GAIN CONTROL CHROMA RESAMPLE LUMA 2D COMB AV CODE INSERTION CHROMA 2D COMB VIDEO DATA OUTPUT MEASUREMENT BL
ADV7189B SYNC PROCESSING GENERAL SETUP The ADV7189B extracts syncs embedded in the video data stream. There is currently no support for external HS/VS inputs. The sync extraction has been optimized to support imperfect video sources such as VCRs with head switches. The actual algorithm used employs a coarse detection based on a threshold crossing followed by a more detailed detection using an adaptive interpolation algorithm.
ADV7189B AD_N443_EN Enable Autodetection of NTSC 443, Address 0x07[5] SFL_INV Subcarrier Frequency Lock Inversion Setting AD_N443_EN to 0 disables the autodetection of NTSC style systems with a 4.43 MHz color subcarrier. Setting AD_N443_EN to 1 (default) enables the detection. This bit controls the behavior of the PAL switch bit in the SFL (GenLock Telegram) data stream. It was implemented to solve some compatibility issues with video encoders.
ADV7189B Table 20. CIL Function SRLS Select Raw Lock Signal, Address 0x51[6] Using the SRLS bit, the user can choose between two sources for determining the lock status (per Bits[1:0] in the Status 1 register). • The time_win signal is based on a line-to-line evaluation of the horizontal synchronization pulse of the incoming video. It reacts quickly. • The free_run signal evaluates the properties of the incoming video over several fields, and takes vertical synchronization information into account.
ADV7189B The hue adjustment value is fed into the AM color demodulation block. Therefore, it only applies to video signals that contain chroma information in the form of an AM modulated carrier (CVBS or Y/C in PAL or NTSC). It does not affect SECAM and does not work on component video inputs (YPrPb). SD_SAT_Cr[7:0] SD Saturation Cr Channel, Address 0xE4[7:0] This register allows the user to control the gain of the Cr channel only. Table 24.
ADV7189B DEF_VAL_EN Default Value Enable, Address 0x0C[0] The clamping can be divided into two sections: This bit forces the use of the default values for Y, Cr, and Cb. Refer to the descriptions for DEF_Y and DEF_C for additional information. In this mode, the decoder also outputs a stable 27 MHz clock, HS, and VS. • Clamping before the ADC (analog domain): current sources. • Clamping after the ADC (digital domain): digital processing block.
ADV7189B The following sections describe the I2C signals that can be used to influence the behavior of the clamping block on the ADV7189B. The luma antialias filter decimates the oversampled video using a high quality, linear phase, low-pass filter that preserves the luma signal while at the same time attenuating out-of-band components. The luma antialias filter (YAA) has a fixed response.
ADV7189B YSFM[4:0] Y-Shaping Filter Mode, Address 0x17[4:0] An automatic mode for Y-shaped filtering is provided. In this mode, the ADV7189B evaluates the quality of the incoming video signal and selects the filter responses in accordance with the signal quality and video standard. YFSM, WYSFMOVR, and WYSFM allow the user to manually override these automatic decisions in part or in full. The Y-shaping filter mode bits allow the user to select from a wide range of low-pass and notch filters.
ADV7189B Table 30.
ADV7189B COMBINED Y ANTIALIAS, NTSC NOTCH FILTERS, Y RESAMPLE COMBINED Y ANTIALIAS, S-VHS LOW-PASS FILTERS, Y RESAMPLE 0 0 –10 AMPLITUDE (dB) –20 –30 –40 –40 04983-0-012 –60 –60 –70 0 2 4 6 8 FREQUENCY (MHz) 10 –70 0 179H 180H COMBINED Y ANTIALIAS, CCIR MODE SHAPING FILTER, Y RESAMPLE 0 –60 Chroma Antialias Filter (CAA). The ADV7189B oversamples the CVBS by a factor of 2 and the Chroma/UV by a factor of 4.
ADV7189B CSFM[2:0] C-Shaping Filter Mode, Address 0x17[7] GAIN OPERATION The C-shaping filter mode bits allow the user to select from a range of low-pass filters, SH1 to SH5, and wideband mode for the chrominance signal. The auto-selection options automatically select from the filter options to give the specified response. (See settings 000 and 001 in Table 32). The gain control within the ADV7189B is done on a purely digital basis. The input ADCs support a 12-bit range, mapped into a 1.
ADV7189B Table 33. AGC Modes Input Video Type Any CVBS Luma Gain Manual gain luma. Dependent on horizontal sync depth. Chroma Gain Manual gain chroma. Dependent on color burst amplitude. Taken from luma path. Dependent on color burst amplitude. Taken from luma path. Dependent on color burst amplitude. Taken from luma path. Dependent on color burst amplitude. Taken from luma path. Taken from luma path. Peak White. Y/C Dependent on horizontal sync depth. Peak White.
ADV7189B For example, program the ADV7189B into manual fixed gain mode with a desired gain of 0.89: Table 38. Betacam Levels 1. Use Equation 1 to convert the gain: 0.89 × 2048 = 1822.72 2. Truncate to integer value: 1822.72 = 1822 Name Y Range 3. Convert to hexadecimal: 1822d = 0x71E 4. Split into two registers and program: Luma Gain Control 1[3:0] = 0x7 Luma Gain Control 2[7:0] = 0x1E 5.
ADV7189B CG[11:0] Chroma Gain, Address 0x2D[3:0]; Address 0x2E[7:0]; CMG[11:0] Chroma Manual Gain, Address 0x2D[3:0]; Address 0x2E[7:0] Chroma Gain[11:0] is a dual-function register. If written to, a desired manual chroma gain can be programmed. This gain becomes active if the CAGC[1:0] mode is switched to manual fixed gain. Refer to Equation 2 for calculating a desired gain. If read back, this register returns the current gain value.
ADV7189B CHROMA TRANSIENT IMPROVEMENT (CTI) The signal bandwidth allocated for chroma is typically much smaller than that of luminance. In the past, this was a valid way to fit a color video signal into a given overall bandwidth because the human eye is less sensitive to chrominance than to luminance. The uneven bandwidth, however, can lead to visual artifacts in sharp color transitions. At the border of two bars of color, both components (luma and chroma) change at the same time (see Figure 18).
ADV7189B DNR_TH[7:0] DNR Noise Threshold, Address 0x50[7:0] NTSC Comb Filter Settings The DNR_TH[7:0] value is an unsigned 8-bit number used to determine the maximum edge that is interpreted as noise and therefore blanked from the luma data. Programming a large value into DNR_TH[7:0] causes the DNR block to interpret even large transients as noise and remove them. The effect on the video data is, therefore, more visible. Used for NTSC-M/J CVBS inputs.
ADV7189B CCMN[2:0] Chroma Comb Mode NTSC, Address 0x38[5:3] Table 46. CCMN Function CCMN[2:0] 0xx (default) Description Adaptive comb mode. Configuration Adaptive 3-line chroma comb for CTAPSN = 01. Adaptive 4-line chroma comb for CTAPSN = 10. Adaptive 5-line chroma comb for CTAPSN = 11. 100 101 Disable chroma comb. Fixed chroma comb (top lines of line memory). 110 Fixed chroma comb (all lines of line memory). 111 Fixed chroma comb (bottom lines of line memory).
ADV7189B CTAPSP[1:0] Chroma Comb Taps PAL, Address 0x39[7:6] Table 49. CTAPSP Function CTAPSP[1:0] 00 01 Description Do not use. PAL chroma comb adapts 5 lines (3 taps) to 3 lines (2 taps); cancels cross luma only. PAL chroma comb adapts 5 lines (5 taps) to 3 lines (3 taps); cancels cross luma and hue error less well. PAL chroma comb adapts 5 lines (5 taps) to 4 lines (4 taps); cancels cross luma and hue error well. 10 11 (default) CCMP[2:0] Chroma Comb Mode PAL, Address 0x39[5:3] Table 50.
ADV7189B AV CODE INSERTION AND CONTROLS This section describes the I2C-based controls that affect: • Insertion of AV codes into the data stream. • Data blanking during the vertical blank interval (VBI). • The range of data values permitted in the output data stream. • In an 8-/10-bit-wide output interface (Cb/Y/Cr/Y interleaved data), the AV codes are defined as FF/00/00/AV, with AV being the transmitted word that contains information about H/V/F.
ADV7189B BL_C_VBI Blank Chroma During VBI, Address 0x04[2] LTA[1:0] Luma Timing Adjust, Address 0x27[1:0] Setting BL_C_VBI high, the Cr and Cb values of all VBI lines are blanked. This is done so any data that may arrive during VBI is not decoded as color and output through Cr and Cb. As a result, it is possible to send VBI lines into the decoder, then output them through an encoder again, undistorted.
ADV7189B SYNCHRONIZATION OUTPUT SIGNALS HSE[10:0] HS End, Address 0x34[2:0], Address 0x36[7:0] HS Configuration The position of this edge is controlled by placing a binary number into HSE[10:0]. The number applied offsets the edge with respect to an internal counter that is reset to 0 immediately after EAV Code FF, 00, 00, XY (see Figure 20). HSE is set to 00000000000b, which is 0 LLC1 clock cycles from count[0].
ADV7189B VS and FIELD Configuration VSBHO VS Begin Horizontal Position Odd, Address 0x32[7] The following controls allow the user to configure the behavior of the VS and FIELD output pins, as well as to generate embedded AV codes: The VSBHO and VSBHE bits select the position within a line at which the VS pin (not the bit in the AV code) becomes active. Some follow-on chips require the VS pin to change state only when HS is high/low.
ADV7189B FIELD 1 525 1 2 3 4 5 6 7 8 9 10 11 12 13 19 20 21 22 OUTPUT VIDEO H V NVBEG[4:0] = 0x5 1BT.656-4 NVEND[4:0] = 0x4 REG 0x04. BIT 7 = 1 F NFTOG[4:0] = 0x3 FIELD 2 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 283 284 285 OUTPUT VIDEO H V NVBEG[4:0] = 0x5 1BT.656-4 NVEND[4:0] = 0x4 REG 0x04. BIT 7 = 1 F 04983-0-021 NFTOG[4:0] = 0x3 1APPLIES IF NEMAVMODE = 0: MUST BE MANUALLY SHIFTED IF NEWAVMODE = 1. Figure 21. NTSC Default (BT.656).
ADV7189B Table 56.
ADV7189B 1 NVENDSIGN ADVANCE END OF VSYNC BY NVEND[4:0] For all NTSC/PAL Vsync timing controls, both the V bit in the AV code and the Vsync on the VS pin are modified. 0 NFTOGDELO NTSC Field Toggle Delay on Odd Field, Address 0xE7[7] DELAY END OF VSYNC BY NVEND[4:0] When NFTOGDELO is 0 (default), there is no delay. NOT VALID FOR USER PROGRAMMING NO Setting NFTOGDELO to 1 delays the field toggle/transition on an odd field by a line relative to NFTOG.
ADV7189B Table 57. Recommended User Settings for PAL (See Figure 27) 215H Register 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0xE8 0xE9 0xEA Register Name Vsync Field Control 1 Vsync Field Control 2 Vsync Field Control 3 Hsync Position. Control 1 Hsync Position. Control 2 Hsync Position.
ADV7189B FIELD 1 622 623 624 1 625 2 3 4 5 6 7 8 9 10 11 23 24 OUTPUT VIDEO HS OUTPUT VS OUTPUT PVBEG[4:0] = 0x1 FIELD OUTPUT PVEND[4:0] = 0x4 PFTOG[4:0] = 0x6 FIELD 2 310 311 312 314 313 315 316 317 318 319 320 321 322 323 336 337 OUTPUT VIDEO HS OUTPUT VS OUTPUT PVEND[4:0] = 0x4 PFTOG[4:0] = 0x6 04983-0-027 PVBEG[4:0] = 0x1 FIELD OUTPUT Figure 27.
ADV7189B 1 PVENDSIGN ADVANCE END OF VSYNC BY PVEND[4:0] For all NTSC/PAL Vsync timing controls, both the V bit in the AV code and the Vsync on the VS pin are modified. 0 PFTOGDELO PAL Field Toggle Delay on Odd Field, Address 0xEA[7] DELAY END OF VSYNC BY PVEND[4:0] When PFTOGDELO is 0 (default), there is no delay. NOT VALID FOR USER PROGRAMMING Setting PFTOGDELO to 1 delays the F toggle/transition on an odd field by a line relative to PFTOG.
ADV7189B SYNC PROCESSING The ADV7189B has two additional sync processing blocks that postprocess the raw synchronization information extracted from the digitized input video. If desired, the blocks can be disabled via the following two I2C bits. The Gemstar-compatible data is not available in the I2C registers, and is inserted into the data stream only during horizontal blanking.
ADV7189B Figure 31 shows the bit correspondence between the analog video waveform and the WSS1/WSS2 registers. WSS2[7:6] are undetermined and should be masked out by software. CRC_ENABLE CRC CGMS-A Sequence, Address 0xB2[2] 217H For certain video sources, the CRC data bits can have an invalid format. In such circumstances, the CRC checksum validation procedure can be disabled. The CGMSD bit goes high if the rising edge of the start bit is detected within a time window.
ADV7189B Closed Caption Data Registers CCAP1[7:0], Address 0x99[7:0], CCAP2[7:0], Address 0x9A[7:0] CGMS Data Registers CGMS1[7:0], Address 0x96[7:0], CGMS2[7:0], Address 0x97[7:0], CGMS3[7:0], Address 0x98[7:0] Figure 34 shows the bit correspondence between the analog video waveform and the CCAP1/CCAP2 registers. CCAP1[7] contains the parity bit from the first word. CCAP2[7] contains the parity bit from the second word. Refer to the GDECAD Gemstar Decode Ancillary Data Format, Address 0x4C[0] section.
ADV7189B Letterbox Detection Incoming video signals may conform to different aspect ratios (16:9 wide screen of 4:3 standard). For certain transmissions in the wide screen format, a digital sequence (WSS) is transmitted with the video signal. If a WSS sequence is provided, the aspect ratio of the video can be derived from the digitally decoded bits WSS contains. In the absence of a WSS sequence, letterbox detection can be used to find wide screen signals.
ADV7189B Each data packet starts immediately after the EAV code of the preceding line. The block is configured via I2C in the following ways: 2H GDECEL[15:0] allow data recovery on selected video lines on even fields to be enabled and disabled. • GDECOL[15:0] enable the data recovery on selected lines for odd fields. • GDECAD configures the way in which data is embedded in the video data stream. Figure 35 and Table 64 show the overall structure of the data packet.
ADV7189B Table 65. Data Byte Allocation 2× 1 1 0 0 Raw Information Bytes Retrieved from the Video Line 4 4 2 2 GDECAD 0 1 0 1 • Gemstar Bit Names • DID. The data identification value is 0x140 (10-bit value). Care has been taken that in 8-bit systems, the 2 LSBs do not carry vital information. • EP and !EP. The EP bit is set to ensure even parity on the data-word D[8:0]. Even parity means there is always an even number of 1s within the D[8:0] bit arrangement. This includes the EP bit.
ADV7189B Table 66.
ADV7189B Table 69.
ADV7189B PAL CCAP Data NTSC CCAP Data Half-byte output mode is selected by setting CDECAD = 0; the full-byte mode is enabled by CDECAD = 1. See the GDECAD Gemstar Decode Ancillary Data Format, Address 0x4C[0] section. The data packet formats are shown in Table 70 and Table 71. Half-byte output mode is selected by setting CDECAD = 0; full-byte output mode is selected by setting CDECAD = 1. See the GDECAD Gemstar Decode Ancillary Data Format, Address 0x4C[0] section.
ADV7189B GDECEL[15:0] Gemstar Decoding Even Lines, Address 0x48[7:0]; Address 0x49[7:0] Table 74. NTSC Line Enable Bits and Corresponding Line Numbering The 16 bits of the GDECEL[15:0] are interpreted as a collection of 16 individual line decode enable signals. Each bit refers to a line of video in an even field. Setting a bit to 1 enables the decoder block to retrieve Gemstar or closed caption-compatible data on that particular line. Setting a bit to 0 prevents the decoder from trying to retrieve data.
ADV7189B 6 Table 75. PAL Line Enable Bits and Corresponding Line Numbering 4 2 0 –2 –4 –6 04983-0-043 –8 –10 –12 2.0 2.5 3.0 3.5 4.0 4.5 5.0 FREQUENCY (MHz) Figure 36. NTSC IF Compensation Filter Responses 6 4 2 0 –2 –4 –6 –8 3.
ADV7189B INTRQ_OP_SEL[1:0], Interrupt Duration Select Address 0x40 (Interrupt Space)[1:0] Interrupt Request Output Operation When an interrupt event occurs, the interrupt pin INTRQ goes low with a programmable duration given by INTRQ_DUR_SEL[1:0]. Table 77. INTRQ_OP_SEL INTRQ_OP_SEL[1:0] 00 (default) 01 10 11 INTRQ_DURSEL[1:0], Interrupt Duration Select Address 0x40 (Interrupt Space)[7:6] Table 76.
ADV7189B PIXEL PORT CONFIGURATION The ADV7189B has a very flexible pixel port that can be configured in a variety of formats to accommodate downstream ICs. Table 79 and Table 80 summarize the various functions that the ADV7189B pins can have in different modes of operation. SWPC Swap Pixel Cr/Cb, Address 0x27[7] The ordering of components, for example, Cr vs. Cb, CHA/B/C, can be changed. Refer to the SWPC Swap Pixel Cr/Cb, Address 0x27[7] section.
ADV7189B MPU PORT DESCRIPTION The R/W bit determines the direction of the data. Logic 0 on the LSB of the first byte means the master writes information to the peripheral. Logic 1 on the LSB of the first byte means the master reads information from the peripheral. The ADV7189B supports a 2-wire (I2C-compatible) serial interface. Two inputs, serial data (SDA) and serial clock (SCLK), carry information between the ADV7189B and the system I2C master controller.
ADV7189B REGISTER ACCESSES I2C SEQUENCER The MPU can write to or read from most of the ADV7189B’s registers, excepting the registers that are read-only or writeonly. The subaddress register determines which register the next read or write operation accesses. All communications with the part through the bus start with an access to the subaddress register.
ADV7189B I2C REGISTER MAPS Table 82.
ADV7189B Register Name Reserved Resample Control Reserved Gemstar Ctrl 1 Gemstar Ctrl 2 Gemstar Ctrl 3 Gemstar Ctrl 4 GemStar Ctrl 5 CTI DNR Ctrl 1 CTI DNR Ctrl 2 Reserved CTI DNR Ctrl 4 Lock Count Reserved Free Run Line Length 1 Reserved VBI Info WSS 1 WSS 2 EDTV 1 EDTV 2 EDTV 3 CGMS 1 CGMS 2 CGMS 3 CCAP 1 CCAP 2 Letterbox 1 Letterbox 2 Letterbox 3 Reserved CRC Enable Reserved ADC Switch 1 ADC Switch 2 Reserved Letterbox Control 1 Letterbox Control 2 Reserved Reserved Reserved SD Offset Cb SD Offset Cr SD
ADV7189B Register Name Drive Strength Reserved IF Comp Control VS Mode Control Reset Value xx01 0101 xxxx xxxx 0000 0000 0000 0000 rw rw rw rw rw Dec 244 245 to 247 248 249 Subaddress Hex 0xF4 0xF5 to 0xF7 0xF8 0xF9 Table 83.
ADV7189B Register Name Vsync Field Control 2 Vsync Field Control 3 Hsync Position Control 1 Hsync Position Control 2 Hsync Position Control 3 Polarity NTSC Comb Control PAL Comb Control ADC Control Reserved Manual Window Control Reserved Resample Control Reserved Gemstar Ctrl 1 Gemstar Ctrl 2 Gemstar Ctrl 3 Gemstar Ctrl 4 Gemstar Ctrl 5 CTI DNR Ctrl 1 CTI DNR Ctrl 2 Reserved CTI DNR Ctrl 4 Lock Count Reserved Free Run Line Length 1 Reserved VBI Info WSS 1 WSS 2 EDTV 1 EDTV 2 EDTV 3 CGMS 1 CGMS 2 CGMS 3 CCAP
ADV7189B Register Name SD Offset Cb SD Offset Cr SD Saturation Cb SD Saturation Cr NTSC V Bit Begin NTSC V Bit End NTSC F Bit Toggle PAL V Bit Begin PAL V Bit End PAL F Bit Toggle Reserved Drive Strength Reserved IF Comp Control VS Mode Control Bit 7 SD_OFF_CB.7 SD_OFF_CR.7 SD_SAT_CB.7 Bit 6 SD_OFF_CB.6 SD_OFF_CR.6 SD_SAT_CB.6 Bit 5 SD_OFF_CB.5 SD_OFF_CR.5 SD_SAT_CB.5 Bit 4 SD_OFF_CB.4 SD_OFF_CR.4 SD_SAT_CB.4 Bit 3 SD_OFF_CB.3 SD_OFF_CR.3 SD_SAT_CB.3 Bit 2 SD_OFF_CB.2 SD_OFF_CR.2 SD_SAT_CB.
ADV7189B I2C INTERRUPT REGISTER MAP The following registers are located in Register Access Page 2. Table 85. Interrupt (Page 2) Register Map Details Subaddress 0x40 Register Interrupt Config 1 Register Access Page 2 Bit Description INTRQ_OP_SEL[1:0]. Interrupt Drive Level Select 7 6 INTRQ_DUR_SEL[1:0]. Interrupt Duration Select Reserved Interrupt Status 1 4 Bit 3 MPU_STIM_INTRQ[1:0]. Manual Interrupt Set Mode 2 1 0 0 1 1 0 0 1 0 1 x x 0 1 0 1 Reserved MV_INTRQ_SEL[1:0].
ADV7189B Subaddress 0x44 Register Interrupt Mask 1 Bit Description SD_LOCK_MSKB 7 6 5 4 Bit 3 2 SD_UNLOCK_MSKB Read/Write Register Register Access Page 2 Reserved Reserved Reserved SD_FR_CHNG_MSKB Reserved Reserved Interrupt Status 2 0 0 1 0 1 0 0 0 0 1 MV_PS_CS_MSKB 0x45 0x46 1 0 1 x x x x x x x x CCAPD_Q x 0 1 Read-Only Register GEMD_Q 0 Register Access Page 2 1 CGMS_CHNGD_Q 0 1 WSS_CHNGD_Q 0 1 Reserved Reserved Reserved MPU_STIM_INTRQ_Q 0x47 Interrupt Clear 2 x x x 0 1
ADV7189B Subaddress 0x48 Register Interrupt Mask 2 Bit Description CCAPD_MSKB 7 6 5 4 Bit 3 2 GEMD_MSKB Read/ Write Register Access Page 2 0x49 Raw Status 3 Read Only Register 0 0 1 0 1 CGMS_CHNGD_MSKB 0 1 WSS_CHNGD_MSKB Reserved Reserved Reserved MPU_STIM_INTRQ_MSKB 1 0 1 0 0 0 0 1 SD_OP_50Hz SD 60/50Hz frame rate at output SD_V_LOCK 0 1 0 1 Register Access Page 2 SD_H_LOCK 0 1 0x4A Interrupt Status 3 Read Only Register Register Access Page 2 Reserved SCM_LOCK SECAM Lock Reserved
ADV7189B Subaddress 0x4B Register Interrupt Clear 3 Bit Description SD_OP_CHNG_CLR 7 6 5 4 Bit 3 2 SD_V_LOCK_CHNG_CLR Write Only Register Register Access Page 2 0 1 SD_AD_CHNG_CLR 0 1 SCM_LOCK_CHNG_CLR 0 1 PAL_SW_LK_CHNG_CLR 0x4C Interrupt Mask 2 0 1 x x 0 1 SD_V_LOCK_CHNG_ MSKB Read / Write Register Register Access Page 2 0 1 SD_H_LOCK_CHNG_ MSKB 0 1 SD_AD_CHNG_ MSKB 0 1 SCM_LOCK_CHNG_ MSKB 0 1 PAL_SW_LK_CHNG_ MSKB Reserved Reserved 0 0 1 0 1 SD_H_LOCK_CHNG_CLR Reserved Rese
ADV7189B The following registers are located in the Common I2C Map and Register Access Page 1. Table 86. Common and Normal (Page 1) Register Map Details Subaddress Register Bit Description 0x00 Input Control INSEL[3:0]. The INSEL bits allow the user to select an input channel as well as the input format. VID_SEL[3:0]. The VID_SEL bits allow the user to select the input video standard.
ADV7189B Subaddress Register Bit Description 0x01 Video Selection Reserved ENVSPROC 7 6 Reserved SD_DUP_AV. Duplicates the AV codes from the luma into the chroma path.
ADV7189B Subaddress Register Bit Description 0x07 Autodetect AD_PAL_EN. PAL B/G/I/H autodetect enable. Enable 7 6 5 Bits 4 3 2 AD_NTSC_EN. NTSC autodetect enable. 1 0 0 1 0 1 AD_PALM_EN. PAL M autodetect enable. 1 Enable Disable 0 1 AD_P60_EN. PAL 60 autodetect enable. Enable Disable 0 1 AD_N443_EN. NTSC443 autodetect enable. Enable Disable 0 1 AD_SECAM_EN. SECAM autodetect enable. Enable Disable 0 1 AD_SEC525_EN. SECAM 525 autodetect enable.
ADV7189B Subaddress Register Bit Description 0x0F Power Reserved 7 6 5 Bits 4 3 2 1 0 0 0 Comments Set to default Notes Management PDBP. Power-down bit priority selects between PWRDN bit or PIN. 0 Chip power down controlled by pin Bit has priority (pin disregarded) Set to default System functional Powered down 1 Reserved PWRDN. Power down places the decoder in a full power-down mode. Reserved RES. Chip reset loads all I2C bits with default values. 0x10 Status Register 1. Read-Only.
ADV7189B Subaddress Register Bit Description 0x15 Digital Clamp Control 1 Reserved DCT[1:0]. Digital clamp timing determines the time constant of the digital fine clamp circuitry. 0x17 Shaping Filter Control Reserved YSFM[4:0]. Selects Y-Shaping Filter mode when in CVBS only mode.
ADV7189B Subaddress Register Bit Description 0x18 Shaping Filter Control 2 WYSFM[4:0]. Wideband Y-Shaping Filter mode allows the user to select which Y-shaping filter is used for the Y component of Y/C, YPbPr, B/W input signals; it is also used when a good quality input CVBS signal is detected. For all other inputs, the Y-shaping filter chosen is controlled by YSFM[4:0]. Reserved WYSFMOVR. Enables the use of automatic WYSFN filter.
ADV7189B Subaddress Register Bit Description 0x27 Pixel Delay Control LTA[1:0]. Luma timing adjust allows the user to specify a timing difference between chroma and luma samples. 7 6 Reserved CTA[2:0]. Chroma timing adjust allows a specified timing difference between the luma and chroma samples 0x2B Misc Gain Control Bits 4 3 2 1 0 0 0 Comments No delay 1 0 Luma 1 clk (37ns) delayed 1 0 Luma 2 clk (74ns) early 1 1 Luma 1 clk (37ns) early 0 0 0 0 0 1 1 1 1 AUTO_PDC_EN.
ADV7189B Subaddress Register Bit Description 0x2D Chroma Gain Control 1 CMG[11:8]. Chroma manual gain can be used to program a desired manual chroma gain. Reading back from this register in AGC mode gives the current gain. Reserved CAGT[1:0]. Chroma automatic gain timing allows adjustment of the chroma AGC tracking speed. 0x2E Chroma Gain Control 2 CMG[7:0]. Chroma manual gain lower 8 bits. See CMG[11:8] for description. 0x2F Luma Gain Control 1 LMG[11:8].
ADV7189B Subaddress Register Bit Description 0x34 HS Position Control 1 HSE[10:8]. HS end allows the positioning of the HS output within the video line. Reserved HSB[10:8]. HS begin allows the positioning of the HS output within the video line. Reserved HSB[7:0] See above, using HSB[10:0] and HSE[10:0], the user can program the position and length of HS output signal. HSE[7:0] See above.
ADV7189B Subaddress Register Bit Description 0x38 NTSC Comb Control YCMN[2:0]. luma comb mode, NTSC. 7 6 CCMN[2:0]. chroma comb mode, NTSC. CTAPSN[1:0]. chroma comb taps, NTSC. 0 0 1 1 5 Bits 4 3 0 0 0 1 1 0 0 0 1 1 1 0 1 1 1 0 1 0 1 Rev.
ADV7189B Subaddress Register Bit Description 0x39 PAL Comb Control YCMP[2:0]. luma comb mode, PAL. 7 6 CCMP[2:0]. chroma comb mode, PAL. CTAPSP[1:0]. chroma comb taps, PAL. 5 Bits 4 3 0 0 0 1 1 0 0 0 1 1 1 0 1 1 1 2 0 1 0 0 0 1 1 1 1 0 1 1 1 0 0 0 1 0 0 0 1 1 0 1 1 0x3A Reserved PWRDN_ADC_2. Enables powerdown of ADC2. 0 0 1 PWRDN_ADC_1. Enables powerdown of ADC1. 0 1 PWRDN_ADC_0. Enables powerdown of ADC0.
ADV7189B Subaddress Register Bit Description 0x41 Resample Control Reserved SFL_INV. Controls the behavior of the PAL switch bit. 7 6 5 0 Bits 4 3 1 0 2 0 1 0 0 0 0 1 Gemstar Control 1 Gemstar Control 2 Reserved. GDECEL[15:8]. See the Comments column. GDECEL[7:0]. See the Comments column 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x4A Gemstar Control 3 GDECOL[15:8]. See the Comments column. 0 0 0 0 0 0 0 0 0x4B Gemstar Control 4 GDECOL[7:0]. See above.
ADV7189B Subaddress Register Bit Description 0x51 Lock Count CIL[2:0]. Count-into-lock determines the number of lines the system must remain in lock before showing a locked status. 5 Bits 4 3 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 0 1 0 1 7 6 COL[2:0]. Count-out-of-lock determines the number of lines the system must remain out-of-lock before showing a lost-locked status. SRLS. Select raw lock signal. Selects the determination of the lock. Status. FSCLE. FSC lock enable.
ADV7189B Subaddress Register Bit Description 0x99 CCAP1 0x9A CCAP2 CCAP1[7:0] Closed caption data register. CCAP2[7:0] Closed caption data register. LB_LCT[7:0] Letterbox data register. (Read Only) (Read Only) 0x9B Letterbox 1 (Read Only) 0x9C Letterbox 2 (Read Only) LB_LCM[7:0] Letterbox 3 (Read Only) LB_LCB[7:0] CRC Enable Write Register Reserved CRC_ENABLE. Enable CRC checksum decoded from CGMS packet to validate CGMSD.
ADV7189B Subaddress Register Bit Description 0xC4 ADC SWITCH 2 ADC2_SW[3:0]. Manual muxing control for ADC2. 0xDC 0xDE 0xDD 0xDF 0xE0 0xE1 Letterbox Control 1 Letterbox Control 2 SD Offset Cb 0xE2 SD Offset Cr 0xE3 SD Saturation Cb SD Saturation Cr 0xE4 Reserved ADC_SW_MAN_EN. Enable manual setting of the input signal muxing. LB_TH[4:0]. Sets the threshold value that determines if a line is black. Reserved Reserved LB_EL[3:0].
ADV7189B Subaddress Register Bit Description 0xE5 NTSC V Bit Begin NVBEG[4:0]. How many lines after lCOUNT rollover to set V high. NVBEGSIGN 7 6 5 Bits 4 3 2 1 0 Comments 0 1 0 1 NTSC default (BT.656) 0 Set to low when manual programming Not suitable for user programming No delay Additional delay by 1 line No delay Additional delay by 1 line NTSC default (BT.
ADV7189B Subaddress Register Bit Description 0xE9 PAL V Bit End PVEND[4:0]. How many lines after lCOUNT rollover to set V low. PVENDSIGN 7 6 5 Bits 4 3 2 1 0 Comments 1 1 0 0 PAL default (BT.656) 1 Set to low when manual programming Not suitable for user programming No delay Additional delay by 1 line No delay Additional delay by 1 line PAL default (BT.656) 0 0 1 PVENDDELE. Delay V bit going low by one line relative to PVEND (even field). PVENDDELO.
ADV7189B Subaddress Register Bit Description 0xF9 VS Mode Control EXTEND_VS_MAX_FREQ 7 6 5 Bits 4 3 2 1 0 Comments 0 Limit maximum Vsync frequency to 66.25 Hz (475 lines/frame) Limit maximum Vsync frequency to 70.09 Hz (449 lines/frame) Limit minimum Vsync frequency to 42.75 Hz (731 lines/frame) Limit minimum Vsync frequency to 39.
ADV7189B I2C PROGRAMMING EXAMPLES EXAMPLES USING 28 MHz CLOCK Mode 1 CVBS Input (Composite Video on AIN5) All standards are supported through autodetect, 10-bit, 4:2:2, ITU-R BT.656 output on P19 to P10. Table 87.
ADV7189B Mode 2 S-Video Input (Y on AIN1 and C on AIN4) All standards are supported through autodetect, 10-bit, ITU-R BT.656 output on P19 to P10. Table 88.
ADV7189B Mode 3 YPrPb Input 525i/625i (Y on AIN2, Pr on AIN3, and Pb on AIN6) All standards are supported through autodetect, 10-bit, ITU-R BT.656 output on P19 to P10. Table 89.
ADV7189B Mode 4 CVBS Tuner Input PAL Only on AIN4 10-bit, ITU-R BT.656 output on P19 to P10. Table 90.
ADV7189B EXAMPLES USING 27 MHz CLOCK Mode 1 CVBS Input (Composite Video on AIN5) All standards are supported through autodetect, 10-bit, 4:2:2, ITU-R BT.656 output on P19 to P10. Table 91. Mode 1 CVBS Input Register Address 0x00 0x03 0x15 0x17 0x3A 0x50 0x0E Register Value 0x04 0x00 0x00 0x41 0x16 0x04 0x80 0x50 0x52 0x58 0x77 0x7C 0x7D 0xD0 0xD5 0xD7 0xE4 0xE9 0xEA 0x0E 0x20 0x18 0xED 0xC5 0x93 0x00 0x48 0xA0 0xEA 0x3E 0x3E 0x0F 0x00 Notes CVBS input on AIN5. Enable 10-bit output on P19 to P10.
ADV7189B Mode 2 S-Video Input (Y on AIN1 and C on AIN4) All standards are supported through autodetect, 10-bit, ITU-R BT.656 output on P19 to P10. Table 92. Mode 2 S-Video Input Register Address 0x00 0x03 0x15 0x3A 0x50 0x0E Register Value 0x06 0x00 0x00 0x12 0x04 0x80 0x50 0x52 0x58 0x77 0x7C 0x7D 0xD0 0xD5 0xD7 0xE4 0xE9 0xEA 0x0E 0x20 0x18 0xED 0xC5 0x93 0x00 0x48 0xA0 0xEA 0x3E 0x3E 0x0F 0x00 Notes Y1 = AIN1, C1 = AIN4. Enable 10-bit output on P19 to P10. Slow down digital clamps. Power down ADC 2.
ADV7189B Mode 4 CVBS Tuner Input PAL Only on AIN4 10-bit, ITU-R BT.656 output on P19 to P10. Table 94. Mode 4 CVBS Tuner Input PAL Only Register Address 0x00 0x03 0x07 0x15 0x17 0x19 0x3A 0x50 0x0E Register Value 0x83 0x00 0x01 0x00 0x41 0xFA 0x16 0x0A 0x80 0x50 0x52 0x58 0x77 0x7C 0x7D 0xD0 0xD5 0xD7 0xE4 0xE9 0xEA 0x0E 0x20 0x18 0xED 0xC5 0x93 0x00 0x48 0xA0 0xEA 0x3E 0x3E 0x0F 0x00 Notes CVBS AIN4 Force PAL only mode. Enable 10-bit output on P19 to P10. Enable PAL autodetection only.
ADV7189B PCB LAYOUT RECOMMENDATIONS It is recommended to use a single ground plane for the entire board. This ground plane should have a space between the analog and digital sections of the PCB (see Figure 42). 26H ADV7189B ANALOG INTERFACE INPUTS ANALOG SECTION Take care when routing the inputs on the PCB. Track lengths should be kept to a minimum, and 75 Ω trace impedances should be used when possible. Trace impedances other than 75 Ω increase the chance of reflections.
ADV7189B DIGITAL INPUTS CRYSTAL LOAD CAPACITOR VALUE SELECTION The digital inputs on the ADV7189B are designed to work with 3.3 V signals, and are not tolerant of 5 V signals. Extra components are needed if 5 V logic signals are required to be applied to the decoder. ANTIALIASING FILTERS For inputs from some video sources that are not bandwidth limited, signals outside the video band can alias back into the video band during A/D conversion and appear as noise on the output video.
ADV7189B TYPICAL CIRCUIT CONNECTION Examples of how to connect the ADV7189B video decoder are shown in Figure 45 and Figure 46. For a detailed schematic diagram for the ADV7189B, refer to the ADV7189B evaluation note. 26H 267H AVDD_5V BUFFER R39 4.7kΩ R38 75Ω R53 56Ω R89 5.6kΩ C B IN Q6 E FILTER L10 12μH OUT R24 470Ω C95 22pF AGND C102 10pF R63 820Ω 04983-0-041 C93 100μF R43 0Ω Figure 45. ADI Recommended Anti-Aliasing Circuit for All Input Channels Rev.
ADV7189B FERRITE BEAD DVDDIO (3.3V) 33μF 10μF PVDD (1.8V) 33μF 10μF 33μF AGND 10μF 33μF 0.1μF AGND 10μF AIN1 AIN7 100nF DVDDIO ANTIALIAS FILTER CIRCUIT DGND AVDD DGND 100nF PVDD DGND 0.1μF DVDD AGND DGND AIN8 AIN3 ANTIALIAS FILTER CIRCUIT AIN9 100nF ADV7189B AIN4 Pb ANTIALIAS FILTER CIRCUIT 100nF CBVS ANTIALIAS FILTER CIRCUIT 100nF AIN10 AIN5 AIN11 75Ω 75Ω 75Ω 75Ω 75Ω 75Ω AIN6 RECOMMENDED ANTIALIAS FILTER CIRCUIT IS SHOWN IN FIGURE 45 ON THE PREVIOUS PAGE.
ADV7189B OUTLINE DIMENSIONS 0.75 0.60 0.45 16.20 16.00 SQ 15.80 1.60 MAX 61 80 60 1 PIN 1 14.20 14.00 SQ 13.80 TOP VIEW (PINS DOWN) 1.45 1.40 1.35 0.15 0.05 0.20 0.09 7° 3.5° 0° 0.10 MAX COPLANARITY SEATING PLANE VIEW A 20 41 40 21 VIEW A 0.65 BSC LEAD PITCH ROTATED 90° CCW 0.38 0.32 0.22 COMPLIANT TO JEDEC STANDARDS MS-026-BEC Figure 47.
ADV7189B NOTES Rev.
ADV7189B NOTES Rev.
ADV7189B NOTES Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04983–0–9/05(B) Rev.