a Professional Extended-10 ™ Video Encoder with 54 MHz Oversampling ADV7194 FEATURES 10-Bit Extended CCIR-656 Input Data Port Six High-Quality 10-Bit Video DACs 10-Bit Internal Digital Video Processing Multistandard Video Input Multistandard Video Output 4ⴛ Oversampling with Internal 54 MHz PLL Programmable Video Control Includes: Digital Noise Reduction Gamma Correction Black Burst LUMA Delay CHROMA Delay Multiple Luma and Chroma Filters Luma SSAF™ (Super Sub-Alias Filter) Average Brightness Detection Fi
ADV7194 REGISTER ACCESSES . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 REGISTER PROGRAMMING . . . . . . . . . . . . . . . . . . . . . 29 MODE REGISTERS 0–9 . . . . . . . . . . . . . . . . . . . . . . . 30–35 TIMING REGISTERS 0–1 . . . . . . . . . . . . . . . . . . . . . . . . 36 SUBCARRIER FREQUENCY AND PHASE REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 CLOSED CAPTIONING REGISTERS . . . . . . . . . . . . . . . 37 NTSC PEDESTAL/PAL TELETEXT CONTROL REGISTERS . . . . . . . .
ADV7194 SPECIFICATIONS (V 1 5 V SPECIFICATIONS = 5 V, VREF = 1.235 V, RSET1,2 = 1200 ⍀ unless otherwise noted. All specifications TMIN to TMAX2 unless otherwise noted.
ADV7194–SPECIFICATIONS 2 1 (VAA = 3.0 V, VREF = 1.235 V, RSET1,2 = 1200 ⍀ unless otherwise noted. All specifications TMIN to TMAX 3.3 V SPECIFICATIONS unless otherwise noted.) Parameter Min Typ STATIC PERFORMANCE Resolution (Each DAC) Accuracy (Each DAC) Integral Nonlinearity Differential Nonlinearity DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN Input Capacitance, CIN Input Leakage Current3 Input Leakage Current4 6 1 200 10 Bits ± 1.0 ± 1.
ADV7194 5 V DYNAMIC SPECIFICATIONS1 Parameter (VAA = 5 V ⴞ 250 mV, VREF = 1.235 V, RSET1,2 = 1200 ⍀ unless otherwise noted. All specifications TMIN to TMAX2 unless otherwise noted.) Min Hue Accuracy Color Saturation Accuracy Chroma Nonlinear Gain Chroma Nonlinear Phase Chroma/Luma Intermod Chroma/Luma Gain Ineq Chroma/Luma Delay Ineq Luminance Nonlinearity Chroma AM Noise Chroma PM Noise Differential Gain3 Differential Phase3 SNR (Pedestal)3 Typ Max 0.5 0.7 0.7 0.5 0.1 1.7 2.2 0.6 82 72 0.1 (0.4) 0.
ADV7194 5 V TIMING CHARACTERISTICS Parameter (VAA = 5 V ⴞ 250 mV, VREF = 1.235 V, RSET1,2 = 1200 ⍀ unless otherwise noted. All specifications TMIN to TMAX1 unless otherwise noted.) Min MPU PORT2 SCLOCK Frequency SCLOCK High Pulsewidth, t1 SCLOCK Low Pulsewidth, t2 Hold Time (Start Condition), t3 Setup Time (Start Condition), t4 Data Setup Time, t5 SDATA, SCLOCK Rise Time, t6 SDATA, SCLOCK Fall Time, t7 Setup Time (Stop Condition), t8 Typ 0 0.6 1.3 0.6 0.
ADV7194 3.3 V TIMING CHARACTERISTICS Parameter Max Unit 400 2 kHz µs µs µs µs ns ns ns µs 8 0.
ADV7194 t5 t3 t3 SDA t6 t1 SCL t2 t7 t4 t8 Figure 1. MPU Port Timing Diagram CLOCK t9 PIXEL INPUT DATA CONTROL O/PS t12 t10 HSYNC, VSYNC, BLANK CONTROL I/PS Cb Y Cr Y t11 HSYNC, VSYNC, BLANK, CSO_HSO, VSO, CLAMP Cb Y t13 t14 Figure 2. Pixel and Control Data Timing Diagram TTXREQ t16 CLOCK t17 t18 TTX 4 CLOCK CYCLES 4 CLOCK CYCLES 4 CLOCK CYCLES 3 CLOCK CYCLES 4 CLOCK CYCLES Figure 3.
ADV7194 ABSOLUTE MAXIMUM RATINGS 1 PACKAGE THERMAL PERFORMANCE VAA to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Voltage on Any Digital Input Pin . . . . GND – 0.5 V to VAA + 0.5 V Storage Temperature (TS) . . . . . . . . . . . . . . –65°C to +150°C Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . . 150°C Body Temperature (Soldering, 10 secs) . . . . . . . . . . . . . 220°C Analog Outputs to GND2 . . . . . . . . . . . . . . GND – 0.
ADV7194 PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Input/ Output 1–10 P0–P9 I 11–20 Y0/P10–Y9/P19 I 10-Bit or 8-Bit 4:2:2 Multiplexed YCrCb Pixel Port. The LSB of the input data is set up on Pin P0 (Pin Number 1) in 10-bit input mode. 20-Bit or 16-Bit Multiplexed YCrCb Pixel Port or 1× 10-bit progressive scan input for Y data. P G Digital Power Supply (3.3 V to 5 V). Digital Ground. I/O HSYNC (Modes 1, 2, and 3) Control Signal.
ADV7194 There are six DACs available on the ADV7194, each of which is capable of providing 4.33 mA of current. In addition to the composite output signal there is the facility to output S-Video (Y/C Video), RGB Video, and YUV Video. All YUV formats (SMPTE/EBU N10, MII, or Betacam) are supported.
ADV7194 Digital noise reduction allows improved picture quality in removing low-amplitude, high-frequency noise. Figure 6 shows the DNR functionality in the two modes available. The output video frames are synchronized with the incoming data timing reference codes. Optionally the encoder accepts (and can generate) HSYNC, VSYNC and FIELD timing signals. These timing signals can be adjusted to change pulsewidth and position while the part is in master mode. Programmable gamma correction is also available.
ADV7194 When used to interface progressive scan systems, the ADV7194 allows input to YCrCb signals in Progressive Scan format (3 × 10 bit) before these signals are routed to the interpolation filters and the DACs. In Extended Mode there is the option of 12 responses in the range from –4 dB to +4 dB. The desired response can be chosen by the user by programming the correct value via the I2C. The variation of frequency responses can be seen in the tables on the following pages.
0 0 –10 –10 –20 –20 MAGNITUDE – dB MAGNITUDE – dB ADV7194 –30 –40 –30 –40 –50 –50 –60 –60 –70 –70 2 0 4 6 8 FREQUENCY – MHz 10 12 0 0 0 –10 –10 –20 –20 –30 –40 10 12 –40 –50 –60 –60 0 6 8 FREQUENCY – MHz –30 –50 –70 4 Figure 13. NTSC Notch Luma Filter MAGNITUDE – dB MAGNITUDE – dB Figure 10. NTSC Low-Pass Luma Filter 2 –70 2 4 6 8 FREQUENCY – MHz 10 2 0 12 Figure 11. PAL Low-Pass Luma Filter 4 6 8 FREQUENCY – MHz 10 12 Figure 14.
ADV7194 1 4 2 MAGNITUDE – dB MAGNITUDE – dB 0 –1 –2 –3 0 –2 –4 –6 –8 –4 –10 –5 0 –12 1 4 3 FREQUENCY – MHz 2 5 6 7 0 0 –10 –10 –20 –20 –30 7 –40 –50 –50 –60 –60 0 –70 2 4 6 8 FREQUENCY – MHz 10 12 0 Figure 17. Luma CIF Filter 0 0 –10 –10 –20 –20 –30 –40 –60 –60 –70 –70 4 6 8 FREQUENCY – MHz 6 8 FREQUENCY – MHz 10 12 10 12 –40 –50 2 4 –30 –50 0 2 Figure 20. Luma QCIF Filter MAGNITUDE – dB MAGNITUDE – dB 6 –30 –40 10 12 Figure 18. Chroma 0.
0 0 –10 –10 –20 –20 MAGNITUDE – dB MAGNITUDE – dB ADV7194 –30 –40 –40 –50 –50 –60 –60 –70 0 2 4 6 8 FREQUENCY – MHz 10 –70 12 Figure 22. Chroma 1.3 MHz Low-Pass Filter 0 0 –10 –10 –20 –20 –30 –40 –60 –60 2 4 6 8 FREQUENCY – MHz 10 4 6 8 FREQUENCY – MHz 10 12 –40 –50 0 2 –30 –50 –70 0 Figure 25. Chroma 2 MHz Low-Pass Filter MAGNITUDE – dB MAGNITUDE – dB –30 –70 12 0 Figure 23. Chroma 3 MHz Low-Pass Filter 2 4 6 8 FREQUENCY – MHz 10 12 Figure 26.
ADV7194 FEATURES—FUNCTIONAL DESCRIPTION CSO, HSO, AND VSO OUTPUTS BLACK BURST OUTPUT It is possible to output a black burst signal from two DACs. This signal output is very useful for professional video equipment since it enables two video sources to be locked together. (Mode Register 9.) The ADV7194 supports three output timing signals, CSO (composite sync signal), HSO (Horizontal Sync Signal) and VSO (Vertical Sync Signal). These output TTL signals are aligned with the analog video outputs.
ADV7194 UNDERSHOOT LIMITER POWER-ON RESET A limiter is placed after the digital filters. This prevents any synchronization problems for TVs. The level of undershoot is programmable between –1.5 IRE, –6 IRE, –11 IRE when operating in 4× Oversampling Mode. In 2× Oversampling Mode the limits are –7.5 IRE and 0 IRE. (Mode Register 9 and Timing Register 0.) After power-up, it is necessary to execute a RESET operation. A reset occurs on the falling edge of a high-to-low transition on the RESET pin.
ADV7194 SCH PHASE MODE ADV7194 The SCH phase is configured in default mode to reset every four (NTSC) or eight (PAL) fields to avoid an accumulation of SCH phase error over time. In an ideal system, zero SCH phase error would be maintained forever, but, in reality, this is impossible to achieve due to clock frequency variations. This effect is reduced by the use of a 32-bit DDS, which generates this SCH.
ADV7194 YUV LEVELS VIDEO TIMING DESCRIPTION This functionality allows the ADV7194 to output SMPTE levels or Betacam levels on the Y output when configured in PAL or NTSC mode. The ADV7194 is intended to interface to off-the-shelf MPEG1 and MPEG2 Decoders.
ADV7194 RESET DAC D, DAC E XXXXXXX XXXXXXX BLACK VALUE WITH SYNC VALID VIDEO DAC F XXXXXXX XXXXXXX BLACK VALUE VALID VIDEO DAC A, DAC B, DAC C XXXXXXX VALID VIDEO OFF MR26 PIXEL_DATA_VALID XXXXXXX DIGITAL TIMING XXXXXXX 1 0 DIGITAL TIMING SIGNALS SUPPRESSED TIMING ACTIVE Figure 36. RESET Sequence Timing Diagram ADV7194 CLOCK GLL LCC1 VIDEO DECODER P19–P10 COMPOSITE VIDEO e.g.
ADV7194 Mode 0 (CCIR–656): Slave Option (Timing Register 0 TR0 = X X X X X 0 0 0) The ADV7194 is controlled by the SAV (Start Active Video) and EAV (End Active Video) Time Codes in the Pixel Data. All timing information is transmitted using a 4-byte synchronization pattern. A synchronization pattern is sent immediately before and after each line during active picture and retrace. Mode 0 is illustrated in Figure 38. The HSYNC, VSYNC and BLANK (if not used) pins should be tied high during this mode.
ADV7194 DISPLAY DISPLAY 622 623 VERTICAL BLANK 624 625 1 2 3 4 5 6 7 21 22 23 H V F EVEN FIELD ODD FIELD DISPLAY DISPLAY VERTICAL BLANK 309 310 311 312 313 314 315 316 317 318 319 320 H V F ODD FIELD EVEN FIELD Figure 40. Timing Mode 0, PAL Master Mode ANALOG VIDEO H F V Figure 41. Timing Mode 0 Data Transitions, Master Mode REV.
ADV7194 Mode 1: Slave Option HSYNC, BLANK, FIELD (Timing Register 0 TR0 = X X X X X 0 1 0) In this mode the ADV7194 accepts Horizontal SYNC and Odd/Even FIELD signals. A transition of the FIELD input when HSYNC is low indicates a new frame, i.e., Vertical Retrace. The BLANK signal is optional. When the BLANK input is disabled the ADV7194 automatically blanks all normally blank lines as per CCIR-624. Mode 1 is illustrated in Figure 42 (NTSC) and Figure 43 (PAL).
ADV7194 Mode 1: Master Option HSYNC, BLANK, FIELD (Timing Register 0 TR0 = X X X X X 0 1 1) In this mode the ADV7194 can generate Horizontal SYNC and Odd/Even FIELD signals. A transition of the FIELD input when HSYNC is low indicates a new frame, i.e., Vertical Retrace. The BLANK signal is optional. When the BLANK input is disabled the ADV7194 automatically blanks all normally blank lines as per CCIR-624. Pixel data is latched on the rising clock edge following the timing signal transitions.
ADV7194 DISPLAY 622 623 DISPLAY VERTICAL BLANK 624 625 1 2 3 4 6 5 7 21 22 23 HSYNC BLANK VSYNC EVEN FIELD ODD FIELD DISPLAY DISPLAY 309 310 VERTICAL BLANK 311 312 313 314 315 316 318 317 319 320 334 335 336 HSYNC BLANK VSYNC ODD FIELD EVEN FIELD Figure 46. Timing Mode 2, PAL Mode 2: Master Option HSYNC, VSYNC, BLANK (Timing Register 0 TR0 = X X X X X 1 0 1) In this mode the ADV7194 can generate Horizontal and Vertical SYNC signals.
ADV7194 Mode 3: Master/Slave Option HSYNC, BLANK, FIELD (Timing Register 0 TR0 = X X X X X 1 1 0 or X X X X X 1 1 1) In this mode the ADV7194 accepts or generates Horizontal SYNC and Odd/Even FIELD signals. A transition of the FIELD input when HSYNC is high indicates a new frame, i.e., Vertical Retrace. The BLANK signal is optional. When the BLANK input is disabled the ADV7194 automatically blanks all normally blank lines as per CCIR-624. Mode 3 is illustrated in Figure 49 (NTSC) and Figure 50 (PAL).
ADV7194 MPU PORT DESCRIPTION The ADV7194 acts as a standard slave device on the bus. The data on the SDA pin is 8 bits long supporting the 7-bit addresses plus the R/W bit. It interprets the first byte as the device address and the second byte as the starting subaddress. The subaddresses autoincrement allowing data to be written to or read from the starting subaddress. A data transfer is always terminated by a stop condition.
ADV7194 REGISTER ACCESSES Subaddress Register (SR7–SR0) The MPU can write to or read from all of the registers of the ADV7194 except the Subaddress Registers which are write only registers. The Subaddress Register determines which register the next read or write operation accesses. All communications with the part through the bus start with an access to the Subaddress Register.
ADV7194 MODE REGISTER 0 MR0 (MR07–MR00) (Address (SR4–SR0) = 00H) MODE REGISTER 1 MR1 (MR17–MR10) (Address (SR4–SR0) = 01H) Figure 55 shows the various operations under the control of Mode Register 0. Figure 56 shows the various operations under the control of Mode Register 1. MR0 BIT DESCRIPTION Output Video Standard Selection (MR00–MR01) MR1 BIT DESCRIPTION DAC Control (MR10–MR15) These bits are used to setup the encoder mode.
ADV7194 Standard I2C Control (MR25) MODE REGISTER 2 MR2 (MR27–MR20) (Address (SR4–SR0) = 02H) This bit controls the video standard used by the ADV7194. When this bit is set to 1 the video standard is as programmed in Mode Register 0 (Output Video Standard Selection). When it is set to 0, the ADV7194 is forced into the standard selected by the NTSC_PAL pin. When NTSC_PAL is low the standard is NTSC, when the NTSC_PAL pin is high, the standard is PAL. Mode Register 2 is an 8-bit-wide register.
ADV7194 MODE REGISTER 3 MR3 (MR37–MR30) (Address (SR4–SR0) = 03H) Genlock Control (MR41–MR42) Mode Register 3 is an 8-bit-wide register. Figure 58 shows the various operations under the control of Mode Register 3. These bits control the Genlock feature and timing reset of the ADV7194 Setting MR41 and MR42 to Logic 0 disables the SCRESET/RTC/TR pin and allows the ADV7194 to operate in normal mode. MR3 BIT DESCRIPTION Revision Code (MR30–MR31) 1.
ADV7194 MR47 MR46 MR45 COLOR BAR CONTROL MR46 0 DISABLE 1 ENABLE INTERLACED MODE CONTROL MR47 0 INTERLACED 1 NONINTERLACED MR44 MR43 CHROMINANCE CONTROL MR44 0 ENABLE COLOR 1 DISABLE COLOR MR42 MR41 MR40 GENLOCK CONTROL MR42 MR41 0 0 0 1 1 1 0 1 DISABLE GENLOCK ENABLE SUBCARRIER RESET PIN TIMING RESET ENABLE RTC PIN BURST CONTROL ACTIVE VIDEO LINE DURATION MR45 0 ENABLE BURST 1 DISABLE BURST MR43 0 720 PIXELS 1 710 PIXELS/702 PIXELS VSYNC 3H CONTROL MR40 0 DISABLE 1 ENABLE Figure 59.
ADV7194 MR67 MR66 MR65 MR64 MR63 MR67 MR66 MR65 MR64 MR63 MR62 FIELD COUNTER ZERO MUST BE WRITTEN TO THESE BITS MR62 MR61 PLL ENABLE CONTROL MR61 0 1 ENABLED DISABLED MR60 POWER-UP SLEEP MODE CONTROL MR60 0 ENABLED 1 DISABLED Figure 61. Mode Register 6, MR6 MODE REGISTER 6 MR6 (MR67–MR60) (ADDRESS (SR4–SR0) = 06H) chrominance component of the composite video signal being clipped if the amplitude of the luma is too high. When this bit is set (0), this control is disabled.
ADV7194 MR87 MR86 MR85 GAMMA ENABLE CONTROL MR86 0 DISABLE 1 ENABLE GAMMA CURVE SELECT CONTROL MR87 0 1 CURVE A CURVE B MR84 MR83 10-BIT PIXEL PORT CONTROL MR84 0 1 MR82 20-/16-BIT PIXEL PORT CONTROL MR83 0 DISABLE 1 ENABLE MR80 PROGRESSIVE SCAN CONTROL MR80 0 DISABLE 1 ENABLE DOUBLE BUFFER CONTROL MR82 0 DISABLE 1 ENABLE DISABLE ENABLE DNR ENABLE CONTROL MR85 0 DISABLE 1 ENABLE MR81 MR81 ZERO MUST BE WRITTEN TO THIS BIT Figure 63.
ADV7194 MR97 MR96 MR97 MR96 ZERO MUST BE WRITTEN TO THESE BITS MR95 MR94 CHROMA DELAY CONTROL MR95 MR94 0 0 1 1 0 1 0 1 0ns DELAY 148ns DELAY 296ns DELAY RESERVED MR93 BLACK BURST LUMA DAC MR93 0 DISABLE 1 ENABLE MR92 MR91 BLACK BURST Y-DAC MR92 0 DISABLE 1 ENABLE MR90 UNDERSHOOT LIMITER MR91 MR90 0 0 1 1 0 1 0 1 DISABLED –11 IRE –6 IRE –1.5 IRE Figure 65.
ADV7194 TR17 TR16 TR15 HSYNC TO PIXEL DATA ADJUST TR15 TR14 0 TPCLK 1 T PCLK 2 TPCLK 3 TPCLK 0 1 0 1 TR13 TR13 TR12 TC 0 1 TR12 TR11 HSYNC TO VSYNC DELAY HSYNC TO VSYNC RISING EDGE DELAY (MODE 1 ONLY) TR17 TR16 0 0 1 1 TR14 0 0 1 1 TB TB + 32 s 0 1 0 1 TR10 HSYNC WIDTH TB TR11 TR10 0 TPCLK 4 T PCLK 8 TPCLK 18 TPCLK 0 0 1 1 0 1 0 1 TA 1 TPCLK 4 T PCLK 16 TPCLK 128 TPCLK VSYNC WIDTH (MODE 2 ONLY) TR15 TR14 0 0 1 1 0 1 0 1 1 TPCLK 4 T PCLK 16 TPC
ADV7194 LINE 17 LINE 16 FIELD 1/3 FIELD 1/3 PCO7 PCO6 TTXREQ Rising Edge Control (TC04–TC07) LINE 15 LINE 14 LINE 13 LINE 12 LINE 11 LINE 10 PCO5 PCO4 PCO3 PCO2 PCO1 LINE 25 LINE 24 LINE 23 LINE 22 LINE 21 LINE 20 PCO15 PCO14 PCO13 PCO12 PCO11 PCO10 These bits control the position of the rising edge of TTXREQ. It can be programmed from zero clock cycles to a maximum of 15 clock cycles. PCO0 LINE 19 LINE 18 PCO9 PCO8 PCLK = clock cycle at 27 MHz.
ADV7194 CGMS_WSS REGISTER 1 C/W1 (C/W17–C/W10) (Address (SR4–SR0) = 1AH) CC07 CC06 CC05 CGMS_WSS register 1 is an 8-bit-wide register. Figure 76 shows the operations under control of this register. CGMS Data (C/W16–C/W17) These bits are CGMS data bits only. C/W15 C/W14 C/W13 C/W12 C/W17 – C/W16 C/W15 – C/W10 CGMS DATA CGMS/WSS DATA C/W11 C/W10 CC07 – CC00 The color control registers are 8-bit-wide registers used to scale the U and V output levels.
ADV7194 HUE ADJUST CONTROL REGISTER (HCR) (Address (SR5–SR0) = 20H) BRIGHTNESS CONTROL REGISTERS (BCR) (Address (SR5–SR0) = 21H) The hue control register is an 8-bit-wide register used to adjust the hue on the composite and chroma outputs. Figure 80 shows the operation under control of this register. The brightness control register is an 8-bit-wide register which allows brightness control. Figure 81 shows the operation under control of this register.
ADV7194 Figures 79 and 80 show the various operations under the control of DNR Register 0. SHARPNESS RESPONSE REGISTER (PR) (Address (SR5–SR0) = 22H) The sharpness response register is an 8-bit-wide register. The four MSBs are set to 0. The four LSBs are written to in order to select a desired filter response. Figure 82 shows the operation under control of this register.
ADV7194 DNR17 BLOCK SIZE CONTROL DNR17 0 1 DNR16 DNR15 DNR14 DNR13 0 1 DNR11 DNR10 DNR THRESHOLD BORDER AREA DNR DNR DNR DNR DNR DNR 15 14 13 12 11 10 DNR16 8 PIXELS 16 PIXELS DNR12 2 PIXELS 4 PIXELS 0 0 • • • 1 1 0 0 • • • 1 1 0 0 • • • 1 1 0 0 • • • 1 1 0 0 • • • 1 1 0 1 • • • 0 1 0 1 • • • 62 63 Figure 86. DNR Register 1 DNR2 BIT DESCRIPTION DNR Input Select (DNR20–DNR22) DNR MODE Three bits are assigned to select the filter which is applied to the incoming Y data.
ADV7194 DNR27 DNR26 DNR25 DNR24 0 0 0 • • • 1 1 1 0 0 0 • • • 1 1 1 0 0 1 • • • 0 1 1 0 1 0 • • • 1 0 1 0 PIXEL OFFSET 1 PIXEL OFFSET 2 PIXEL OFFSET • • • 13 PIXEL OFFSET 14 PIXEL OFFSET 15 PIXEL OFFSET DNR22 DNR MODE CONTROL BLOCK OFFSET CONTROL DNR DNR DNR DNR 27 26 25 24 DNR23 DNR21 DNR20 DNR INPUT SELECT CONTROL DNR DNR DNR 22 21 20 DNR23 0 DNR MODE 1 DNR SHARPNESS MODE 0 0 0 1 0 1 1 0 1 0 1 0 FILTER A FILTER B FILTER C FILTER D Figure 90.
ADV7194 BRIGHTNESS DETECT REGISTER (Address (SR5–SR0) = 34H) OCR BIT DESCRIPTION Reserved (OCR00) The Brightness Detect Register is an 8-bit-wide register used only to read back data in order to monitor the brightness/darkness of the incoming video data on a field-by-field basis. The brightness information is read from the I2C and based on this information, the color controls or the gamma correction controls may be adjusted. A Logic 0 must be written to this bit.
ADV7194 APPENDIX 1 BOARD DESIGN AND LAYOUT CONSIDERATIONS Supply Decoupling The ADV7194 is a highly integrated circuit containing both precision analog and high-speed digital circuitry. It has been designed to minimize interference effects on the integrity of the analog circuitry by the high-speed digital circuitry. It is imperative that these same design and layout techniques be applied to the system level design such that high-speed, accurate performance is achieved.
ADV7194 POWER SUPPLY DECOUPLING FOR EACH POWER SUPPLY GROUP 5V (VAA) 10nF 5V (VAA) 0.1 F 5V (VAA) 5V (VAA) COMP2 53, 48, 38 0.1 F 0.1 F COMP1 VAA VREF 79, 68, 34, 21 0.1 F VDD DAC A 300 Cb0 – Cb9 Cr0 – Cr9 10nF DAC B 300 ADV7194 Y0/P10 – Y9/P19 DAC C 300 UNUSED INPUTS SHOULD BE GROUNDED P9 – P0 DAC D 300 CSO_HSO VSO/TTX/CLAMP DAC E PAL_NTSC 300 SCRESET/RTC/TR DAC F HSYNC 5V (VAA) 100 BLANK 4.
ADV7194 APPENDIX 2 CLOSED CAPTIONING FCC Code of Federal Regulations (CFR) 47 Section 15.119 and EIA608 describe the closed captioning information for Lines 21 and 284. The ADV7194 supports closed captioning conforming to the standard television synchronizing waveform for color transmission. Closed captioning is transmitted during the blanked active line time of Line 21 of the odd fields and Line 284 of even fields. The ADV7194 uses a single buffering method.
ADV7194 APPENDIX 3 COPY GENERATION MANAGEMENT SYSTEM (CGMS) The ADV7194 supports Copy Generation Management System (CGMS) conforming to the standard. CGMS data is transmitted on Line 20 of the odd fields and Line 283 of even fields. Bits C/W05 and C/W06 control whether or not CGMS data is put out on ODD and EVEN fields. CGMS data can only be transmitted when the ADV7194 is configured in NTSC mode. The CGMS data is 20 bits long, the function of each of these bits is as shown below.
ADV7194 APPENDIX 4 WIDE SCREEN SIGNALING The ADV7194 supports Wide Screen Signalling (WSS) conforming to the standard. WSS data is transmitted on Line 23. WSS data can only be transmitted when the ADV7194 is configured in PAL mode. The WSS data is 14 bits long, the function of each of these bits is as shown below. The WSS data is preceded by a run-in sequence and a Start Code, see Figure 97.
ADV7194 APPENDIX 5 TELETEXT INSERTION Time, tPD, is the time needed by the ADV7194 to interpolate input data on TTX and insert it onto the CVBS or Y outputs, such that it appears TSYNTTXOUT = 10.2 µs after the leading edge of the horizontal signal. Time TTXDEL is the pipeline delay time by the source that is gated by the TTXREQ signal in order to deliver TTX data.
ADV7194 APPENDIX 6 OPTIONAL OUTPUT FILTER If an output filter is required for the CVBS, Y, UV, Chroma and RGB outputs of the ADV7194, the following filter in Figure 100 can be used in 2× Oversampling Mode. In 4× Oversampling Mode the filter in Figure 102 is recommended. The plot of the filter characteristics are shown in Figures 101 and 103.
ADV7194 APPENDIX 7 DAC BUFFERING External buffering is needed on the ADV7194 DAC outputs. The configuration in Figure 105 is recommended. +VCC When calculating absolute output full-scale current and voltage use the following equations: INPUT/ OPTIONAL FILTER O/P VOUT = IOUT × RLOAD AD8051 OUTPUT TO TV MONITOR –VCC IOUT = (VREF × K)/RSET Figure 106. Recommended DAC Output Buffer Using an Op Amp K = 4.2146 constant, VREF = 1.235 V VAA ADV7194 VREF RSET1 1.
ADV7194 APPENDIX 8 RECOMMENDED REGISTER VALUES The ADV7194 registers can be set depending on the user standard required. The following examples give the various register formats for several video standards. PAL B, D, G, H, I (FSC = 4.43361875 MHz) NTSC (FSC = 3.
ADV7194 PAL 60 (FSC = 4.43361875 MHz) PAL N (FSC = 4.
ADV7194 POWER-ON RESET REGISTER VALUES POWER-ON RESET REG VALUES (PAL_NTSC = 0, NTSC Selected) Address 00Hex 01Hex 02Hex 03Hex 04Hex 05Hex 06Hex 07Hex 08Hex 09Hex 0AHex 0BHex 0CHex 0DHex 0EHex 0FHex 10Hex 11Hex 12Hex 13Hex 14Hex 15Hex 16Hex 17Hex 18Hex 19Hex 1AHex 1BHex 1CHex 1DHex 1EHex 1FHex 20Hex 21Hex 22Hex 23Hex 24Hex 25Hex 26Hex 27Hex 28Hex 29Hex 2AHex 2BHex 2CHex 2DHex 2EHex 2FHex 30Hex 31Hex 32Hex 33Hex 34Hex 35Hex REV.
ADV7194 APPENDIX 9 NTSC WAVEFORMS (WITH PEDESTAL) 130.8 IRE PEAK COMPOSITE 1268.1mV 100 IRE REF WHITE 1048.4mV 714.2mV 387.6mV 334.2mV 7.5 IRE 0 IRE BLACK LEVEL BLANK LEVEL –40 IRE SYNC LEVEL 48.3mV REF WHITE 1048.4mV Figure 107. NTSC Composite Video Levels 100 IRE 714.2mV 7.5 IRE 0 IRE BLACK LEVEL BLANK LEVEL –40 IRE SYNC LEVEL 387.6mV 334.2mV 48.3mV Figure 108. NTSC Luma Video Levels PEAK CHROMA 963.8mV 629.7mV (pk-pk) 286mV (pk-pk) 650mV BLANK/BLACK LEVEL PEAK CHROMA 335.
ADV7194 NTSC WAVEFORMS (WITHOUT PEDESTAL) 130.8 IRE PEAK COMPOSITE 1289.8mV 100 IRE REF WHITE 1052.2mV 714.2mV 0 IRE BLANK/BLACK LEVEL 338mV –40 IRE SYNC LEVEL 52.1mV Figure 111. NTSC Composite Video Levels 100 IRE REF WHITE 1052.2mV 714.2mV 0 IRE BLANK/BLACK LEVEL SYNC LEVEL –40 IRE 338mV 52.1mV Figure 112. NTSC Luma Video Levels PEAK CHROMA 978mV 694.9mV (pk-pk) 286mV (pk-pk) 650mV BLANK/BLACK LEVEL 283mV PEAK CHROMA 0mV Figure 113.
ADV7194 PAL WAVEFORMS PEAK COMPOSITE 1284.2mV 1047.1mV REF WHITE 696.4mV 350.7mV BLANK/BLACK LEVEL 50.8mV SYNC LEVEL Figure 115. PAL Composite Video Levels REF WHITE 1047mV 696.4mV BLANK/BLACK LEVEL 350.7mV SYNC LEVEL 50.8mV Figure 116. PAL Luma Video Levels PEAK CHROMA 990mV 672mV (pk-pk) 300mV (pk-pk) 650mV BLANK/BLACK LEVEL 318mV PEAK CHROMA 0mV Figure 117. PAL Chroma Video Levels REF WHITE 1050.2mV 698.4mV BLANK/BLACK LEVEL 351.8mV SYNC LEVEL 51mV Figure 118.
ADV7194 PARADE SMPTE/EBU PAL mV Y(A) Pb(B) mV Pr(C) mV 700 250 250 600 200 200 500 150 150 400 100 100 300 50 50 200 0 0 –50 –50 0 –100 –100 100 –150 –150 200 –200 –200 –250 –250 100 300 Figure 119. PAL YUV Parade Plot mV GREEN (A) mV BLUE (B) 700 700 600 600 500 500 400 400 300 300 200 200 100 100 0 mV RED (C) 700 600 500 400 300 200 100 0 0 100 100 100 200 200 200 300 300 300 Figure 120. PAL RGB Waveforms REV.
ADV7194 505mV BLACK BLUE RED MAGENTA GREEN CYAN YELLOW WHITE BLACK BLUE RED MAGENTA GREEN CYAN WHITE YELLOW UV WAVEFORMS 505mV 423mV 334mV 171mV BETACAM LEVEL BETACAM LEVEL 82mV 0mV 0mV 0mV 0mV –82mV 171mV 334mV –423mV 505mV –505mV BLACK BLUE RED MAGENTA GREEN CYAN YELLOW WHITE Figure 124. NTSC 100% Color Bars No Pedestal V Levels BLACK BLUE RED MAGENTA GREEN CYAN WHITE YELLOW Figure 121.
ADV7194 OUTPUT WAVEFORMS 0.6 VOLTS 0.4 0.2 0.0 0.2 L608 0.0 10.0 20.0 30.0 40.0 50.0 60.0 MICROSECONDS NOISE REDUCTION: 0.00 dB APL = 39.1% 625 LINE PAL NO FILTERING PRECISION MODE OFF SYNCHRONOUS SLOW CLAMP TO 0.00 V AT 6.72 s SOUND-IN-SYNC OFF SYNC = SOURCE FRAMES SELECTED: 1 2 3 4 Figure 127. 100/0/75/0 PAL Color Bars VOLTS 0.5 0.0 L575 0.0 10.0 APL NEEDS SYNC = SOURCE! 625 LINE PAL NO FILTERING 20.0 30.0 40.0 50.
ADV7194 VOLTS 0.5 0.0 –0.5 L575 10.0 20.0 30.0 40.0 MICROSECONDS APL NEEDS SYNC = SOURCE! 625 LINE PAL NO FILTERING 50.0 60.0 NO BRUCH SIGNAL PRECISION MODE OFF SYNCHRONOUS SLOW CLAMP TO 0.00 V AT 6.72 s SOUND-IN-SYNC OFF SYNC = A FRAMES SELECTED: 1 Figure 129. 100/0/75/0 PAL Color Bars Chrominance 100.0 VOLTS IRE:FLT 0.5 50.0 0.0 0.0 –50.0 0.0 F1 L76 10.0 20.0 30.0 40.0 MICROSECONDS APL = 44.6% 525 LINE NTSC 50.0 60.
ADV7194 100.0 0.6 0.4 VOLTS IRE:FLT 50.0 0.2 0.0 0.0 –0.2 F2 L238 10.0 20.0 30.0 40.0 MICROSECONDS NOISE REDUCTION: 15.05dB APL = 44.7% 525 LINE NTSC NO FILTERING 50.0 PRECISION MODE OFF SYNCHRONOUS SLOW CLAMP TO 0.00 V AT 6.72 s 60.0 SYNC = SOURCE FRAMES SELECTED: 1 2 Figure 131. 100/7.5/75/7.5 NTSC Color Bars Luminance 0.4 50.0 0.0 IRE:FLT VOLTS 0.2 –0.2 –50.0 –0.4 F1 L76 0.0 10.0 20.0 30.0 40.0 MICROSECONDS NOISE REDUCTION: 15.
ADV7194 VIDEO MEASUREMENT PLOTS COLOR BAR (NTSC) FIELD = 1 LINE = 21 WFM FCC COLOR BAR LUMINANCE LEVEL (IRE) 99.6 69.0 55.9 48.1 36.3 28.3 15.7 7.7 GRAY YELLOW CYAN GREEN MAGENTA RED BLUE BLACK 100 50 0 CHROMINANCE LEVEL (IRE) 0.0 62.1 87.6 81.8 81.8 87.8 62.1 0.0 GRAY YELLOW CYAN GREEN MAGENTA RED BLUE BLACK 167.3 283.8 240.9 60.8 103.6 347.
ADV7194 DG DP (NTSC) MOD 5 STEP WFM DG DP (PAL) FIELD = 1, LINE = 21 2.5 0.21 0.02 0.07 0.27 MIN = 0.00, MAX = 0.32, p-p = 0.32 DIIFFERENTIAL GAIN (PERCENT) MIN = 0.00, MAX = 0.27, p-p/MAX = 0.27 DIIFFERENTIAL GAIN (PERCENT) 0.00 MOD 5 STEP WFM LINE = 570 0.08 2.5 0.00 0.30 0.15 0.24 0.32 0.26 1st 2nd 3rd 4th 5th 6th 1.5 1.5 0.5 0.5 –0.5 –0.5 –1.5 –1.5 –2.5 1st 2nd 3rd 4th 2.5 0.10 –2.5 6th 0.12 0.15 0.13 MIN = 0.00, MAX = 0.16, p-p = 0.
ADV7194 CHROMINANCE NONLINEARITY(NTSC) WFM FIELD = 2, LINE = 217 CHROMINANCE AMPLITUDE ERROR (PERCENT) 0.5 NTSC–7 COMBINATION CHROMINANCE NONLINEARITY(PAL) WFM LINE = 572 CHROMINANCE AMPLITUDE ERROR (PERCENT) REF = 40IRE PACKET 0.0 –0.3 MOD 3 STEP REF = 420mV PACKET 0.6 0.0 –0.4 140mV 420mV 700mV 10 10 0 0 –10 –10 20IRE 40IRE 80IRE CHROMINANCE PHASE ERROR (DEGREE) –0.0 5 REF = 40IRE PACKET 0.0 CHROMINANCE PHASE ERROR (DEGREE) 0.
ADV7194 NOISE SPECTRUM (NTSC) PEDESTAL WFM NOISE SPECTRUM (PAL) PEDESTAL WFM LINE = 511 FIELD = 2, LINE = 223 NOISE LEVEL = –79.7dB RMS AMPLITUDE (0dB = 714mV p-p) NOISE LEVEL = –79.1dB RMS AMPLITUDE (0dB = 700mV p-p) BANDWIDTH 10kHz TO FULL BANDWIDTH 10kHz TO FULL 20 0 0 –20 –20 –40 –40 –60 –60 –80 –80 –100 –100 1 2 3 MHz 4 5 6 1 RAMP WFM 5 6 7 NOISE SPECTRUM (PAL) RAMP WFM LINE = 572 NOISE LEVEL = –63.
ADV7194 APPENDIX 10 VECTOR PLOTS V APL = 39.6% SYSTEM LINE L608 ANGLE (DEG) 0.0 GAIN 1.000 0.000dB 625 LINE PAL BURST FROM SOURCE DISPLAY +V AND –V cy R g M g 75% 100% YI b U yl B G Cy m g r SOUND IN SYNC OFF Figure 147. PAL Vector Plot R-Y APL = 45.1% SYSTEM LINE L76F1 ANGLE (DEG) 0.0 GAIN 1.000 0.000dB 525 LINE NTSC BURST FROM SOURCE cy I R M g YI Q b 100% B-Y 75% B G Cy –Q –I SETUP 7.5% Figure 148. NTSC Vector Plot –68– REV.
ADV7194 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 0.063 (1.60) MAX 0.030 (0.75) 0.020 (0.50) C00231–0–2/01 (rev. A) 80-Lead LQFP (ST-80) 0.640 (16.25) SQ 0.620 (15.75) 0.553 (14.05) SQ 0.549 (13.95) 80 1 61 60 SEATING PLANE 0.486 (12.35) TYP SQ TOP VIEW (PINS DOWN) 20 21 41 40 0.029 (0.73) 0.022 (0.57) 0.014 (0.35) 0.010 (0.25) PRINTED IN U.S.A. 0.004 (0.10) MAX 0.006 (0.15) 0.002 (0.05) 0.057 (1.45) 0.053 (1.35) REV.