Datasheet

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Multiformat 216 MHz

Video Encoder with Six NSV

12-Bit DACs

ADV7320/ADV7321

Rev. A

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FEATURES

High definition (HD) input formats

16-/20-, 24-/30-bit (4:2:2, 4:4:4) parallel YCrCb

Fully compliant with

SMPTE 274M (1080i, 1080p @ 74.25 MHz)

SMPTE 296M (720p)

SMPTE 240M (1035i)

RGB in 3-bit × 10-bit 4:4:4 input format

HDTV RGB supported

RGB, RGBHV

Other HD formats using async timing mode

Enhanced definition (ED) input formats

8-/10-, 16-/20-, 24-/30-bit (4:2:2, 4:4:4) parallel YCrCb

SMPTE 293M (525p)

BTA T-1004 EDTV2 (525p)

ITU-R BT.1358 (625p/525p)

ITU-R BT.1362 (625p/525p)

RGB in 3-bit × 10-bit 4:4:4 input format

Standard definition (SD) input formats

CCIR-656 4:2:2 8-/10-bit or 16-/20-bit parallel input

HD output formats

YPrPb HDTV (EIA 770.3)

RGB, RGBHV

CGMS-A (720p/1080i)

ED output formats

Macrovision® Rev 1.2 (525p/625p) (ADV7320 only)

CGMS-A (525p/625p)

YPrPb progressive scan (PS) (EIA-770.1, EIA-770.2)

RGB, RGBHV

SD output formats

Composite NTSC M/N

Composite PAL M/N/B/D/G/H/I, PAL-60

SMPTE 170M NTSC-compatible composite video

ITU-R BT.470 PAL-compatible composite video

S-video (Y/C)

EuroScart RGB

Component YPrPb (Betacam, MII, SMPTE/EBU N10)

Macrovision Rev 7.1.L1 (ADV7320 only)

CGMS/WSS

Closed captioning

GENERAL FEATURES

Simultaneous SD/HD or PS/SD inputs and outputs

Oversampling up to 216 MHz

Programmable DAC gain control

Sync outputs in all modes

On-board voltage reference

Six 12-bit NSV (noise shaped video) precision video DACs

2-wire serial I

C® interface, open-drain configuration

Dual I/O supply 2.5 V/3.3 V operation

Analog and digital supply 2.5 V

On-board PLL

64-lead LQFP package

Lead (Pb) free product

APPLICATIONS

EVD (enhanced versatile disk) players

High-end SD/PS DVD recorders/players

SD/PS/HDTV display devices

SD/HDTV set top boxes

Professional video systems

FUNCTIONAL BLOCK DIAGRAM

CLKIN_

CLKIN_B

HSYNC

VSYNC

BLANK

Y9–Y0

C9–C0

S9–S0

TIMING

GENERATOR

PLL

INTERFACE

STANDARD DEFINITION

CONTROL BLOCK

COLOR CONTROL

BRIGHTNESS

DNR

GAMMA

PROGRAMMABLE

FILTERS

SD TEST PATTERN

HIGH DEFINITION

CONTROL BLOCK

HD TEST PATTERN

COLOR CONTROL

ADAPTIVE FILTER CTRL

SHARPNESS FILTER

PROGRAMMABLE

RGB MATRIX

12-BIT

DAC

12-BIT

DAC

12-BIT

DAC

12-BIT

DAC

12-BIT

DAC

12-BIT

DAC

ADV7320/

ADV7321

05067-001

Figure 1.

GENERAL DESCRIPTION

The ADV®7320/ADV7321 are high speed, digital-to-analog

encoders on single monolithic chips. They include six high

speed NSV video DACs with TTL-compatible inputs. They have

separate 8-/10-, 16-/20-, and 24-/30-bit input ports that accept

data in high definition (HD) and/or standard definition (SD)

video format. For all standards, external horizontal, vertical,

and blanking signals, or EAV/SAV timing codes, control the

insertion of appropriate synchronization signals into the digital

data stream and, therefore, the output signal.

Summary of content (88 pages)

PAGE 1
Multiformat 216 MHz Video Encoder with Six NSV® 12-Bit DACs ADV7320/ADV7321 High definition (HD) input formats 16-/20-, 24-/30-bit (4:2:2, 4:4:4) parallel YCrCb Fully compliant with SMPTE 274M (1080i, 1080p @ 74.
PAGE 2
ADV7320/ADV7321 TABLE OF CONTENTS Features .............................................................................................. 1 Reset Sequence ........................................................................... 45 General Features ............................................................................... 1 SD VCR FF/RW Sync ................................................................ 45 Applications.............................................................................
PAGE 3
ADV7320/ADV7321 CGMS Functionality...................................................................65 Appendix 2—SD Wide Screen Signaling .....................................68 Mode 2—Master Option (Timing Register 0 TR0 = X X X X X 1 0 1) ............................79 Appendix 3—SD Closed Captioning............................................69 Mode 3—Master/Slave Option (Timing Register 0 TR0 = X X X X X 1 1 0 or X X X X X 1 1 1)...80 Appendix 4—Test Patterns.......................................
PAGE 4
ADV7320/ADV7321 Table 1. Standards Directly Supported 1 DETAILED FEATURES HD programmable features (720p/1080i/1035i) 2× oversampling (148.
PAGE 5
ADV7320/ADV7321 HD PIXEL INPUT CLKIN_B Y DEINTER- CR LEAVE CB TEST PATTERN SHARPNESS AND ADAPTIVE FILTER CONTROL Y COLOR CR COLOR CB COLOR 4:2:2 TO 4:4:4 PS 8× HDTV 2× DAC DAC TIMING GENERATOR S_HSYNC S_VSYNC S_BLANK CLKIN_A SD PIXEL INPUT CLOCK CONTROL AND PLL DAC U V TIMING GENERATOR UV SSAF RGB MATRIX DAC SD 16× CB DEINTER- CR LEAVE Y TEST PATTERN DNR GAMMA COLOR CONTROL SYNC INSERTION LUMA AND CHROMA FILTERS 2× OVERSAMPLING FSC MODULATION CGMS WSS DAC DAC 05067-002 P_HSYNC P_V
PAGE 6
ADV7320/ADV7321 SPECIFICATIONS VAA = 2.375 V to 2.625 V, VDD = 2.375 V to 2.625 V, VDD_IO = 2.375 V to 3.6 V, VREF = 1.235 V, RSET = 3040 Ω, RLOAD = 300 Ω. All specifications TMIN to TMAX (0°C to 70°C), unless otherwise noted. Table 2.
PAGE 7
ADV7320/ADV7321 DYNAMIC SPECIFICATIONS VAA = 2.375 V to 2.625 V, VDD = 2.375 V to 2.625 V, VDD_IO = 2.375 V to 3.6 V, VREF = 1.235 V, RSET = 3040 Ω, RLOAD = 300 Ω. All specifications TMIN to TMAX (0°C to 70°C), unless otherwise noted. Table 3.
PAGE 8
ADV7320/ADV7321 TIMING SPECIFICATIONS VAA = 2.375 V to 2.625 V, VDD = 2.375 V to 2.625 V, VDD_IO = 2.375 V to 3.6 V, VREF = 1.235 V, RSET = 3040 Ω, RLOAD = 300 Ω. All specifications TMIN to TMAX (0°C to 70°C), unless otherwise noted. Table 4.
PAGE 9
ADV7320/ADV7321 TIMING DIAGRAMS CLKIN_A t9 CONTROL INPUTS t12 t10 P_HSYNC, P_VSYNC, P_BLANK Y9–Y0 Y0 Y1 Y2 Y3 Y4 Y5 C9–C0 Cb0 Cr0 Cb2 Cr2 Cb4 Cr4 t11 t13 CONTROL OUTPUTS t14 05067-003 t9 = CLOCK HIGH TIME t10 = CLOCK LOW TIME t11 = DATA SETUP TIME t12 = DATA HOLD TIME t13 = HD OUTPUT ACCESS TIME t14 = HD OUTPUT HOLD TIME Figure 3.
PAGE 10
ADV7320/ADV7321 CLKIN_A t9 CONTROL INPUTS t12 t10 P_HSYNC, P_VSYNC, P_BLANK Y9–Y0 G0 G1 G2 G3 G4 G5 C9–C0 B0 B1 B2 B3 B4 B5 R2 R3 R4 R5 t11 S9–S0 R0 R1 CONTROL OUTPUTS t14 t9 = CLOCK HIGH TIME t10 = CLOCK LOW TIME t11 = DATA SETUP TIME t12 = DATA HOLD TIME t13 = HD OUTPUT ACCESS TIME t14 = HD OUTPUT HOLD TIME 05067-005 t13 Figure 5.
PAGE 11
ADV7320/ADV7321 CLKIN_A t10 t9 CONTROL INPUTS P_VSYNC, P_HSYNC, P_BLANK Cb0 Y9–Y0 Yxxx t13 t12 t11 Crxxx Y1 Cr0 Y0 t14 CONTROL OUTPUTS 05067-007 t9 = CLOCK HIGH TIME t10 = CLOCK LOW TIME t11 = DATA SETUP TIME t12 = DATA HOLD TIME t13 = HD OUTPUT ACCESS TIME t14 = HD OUTPUT HOLD TIME Figure 7.
PAGE 12
ADV7320/ADV7321 CLKIN_B t9 CONTROL INPUTS t12 t10 P_HSYNC, P_VSYNC, P_BLANK Y9–Y0 Y0 Y1 Y2 Y3 Y4 Y5 C9–C0 Cb0 Cr0 Cb2 Cr2 Cb4 Cr4 HD INPUT t11 CLKIN_A CONTROL INPUTS S_HSYNC, S_VSYNC, S_BLANK S9–S0 t9 t12 t10 SD INPUT Cr0 Y0 Cb0 Y1 Cb1 Y2 t11 05067-010 t9 = CLOCK HIGH TIME t10 = CLOCK LOW TIME t11 = DATA SETUP TIME t12 = DATA HOLD TIME Figure 10.
PAGE 13
ADV7320/ADV7321 CLKIN_B t9 CONTROL INPUTS t10 P_HSYNC, P_VSYNC, P_BLANK PS INPUT Y9–Y0 Cb0 Cr0 Y0 Crxxx Y1 t12 Yxxx t12 t11 t11 CLKIN_A CONTROL INPUTS t9 S_HSYNC, S_VSYNC, S_BLANK t12 t10 SD INPUT S9–S0 Cr0 Y0 Cb0 Y1 Cb1 Y2 t11 05067-012 t9 = CLOCK HIGH TIME t10 = CLOCK LOW TIME t11 = DATA SETUP TIME t12 = DATA HOLD TIME Figure 12.
PAGE 14
ADV7320/ADV7321 CLKIN_A t9 CONTROL INPUTS t12 t10 S_HSYNC, S_VSYNC, S_BLANK S9–S0/Y9–Y0* C9–C0 IN SLAVE MODE Y0 Cb0 t11 Y1 Y2 Y3 Cr0 Cb2 Cr2 t13 CONTROL OUTPUTS IN MASTER/SLAVE MODE t14 *SELECTED BY ADDRESS 0x01, BIT 7: SEE TABLE 21. 05067-014 t9 = CLOCK HIGH TIME t10 = CLOCK LOW TIME t11 = DATA SETUP TIME t12 = DATA HOLD TIME t13 = HD OUTPUT ACCESS TIME t14 = HD OUTPUT HOLD TIME Figure 14.
PAGE 15
ADV7320/ADV7321 P_HSYNC P_VSYNC a P_BLANK Y9–Y0 Cb Cr Y Y b 05067-016 a = 32 CLKCYCLES FOR 525p a = 24 CLKCYCLES FOR 625p AS RECOMMENDED BY STANDARD b(MIN) = 244 CLKCYCLES FOR 525p b(MIN) = 264 CLKCYCLES FOR 625p Figure 16. PS 4:2:2 10-Bit Interleaved Input Timing Diagram S_HSYNC S_VSYNC PAL = 24 CLK CYCLES NTSC = 32 CLK CYCLES S_BLANK S9–S0/Y9–Y0* Cb Y Cr 05067-017 PAL = 264 CLOCK CYCLES NTSC = 244 CLOCK CYCLES *SELECTED BY ADDRESS 0x01, BIT 7: SEE TABLE 21. Figure 17.
PAGE 16
ADV7320/ADV7321 ABSOLUTE MAXIMUM RATINGS Table 5. Parameter 1 VAA to AGND VDD to DGND VDD_IO to GND_IO Digital Input Voltage to DGND VAA to VDD AGND to DGND DGND to GND_IO AGND to GND_IO Ambient Operating Temperature (TA) Storage Temperature (TS) Infrared Reflow Soldering (20 sec) 1 Value −0.3 V to +3.0 V −0.3 V to +3.0 V −0.3 V to +4.6 V −0.3 V to VDD_IO +0.3 V −0.3 V to +0.3 V −0.3 V to +0.3 V −0.3 V to +0.3 V −0.3 V to +0.
PAGE 17
ADV7320/ADV7321 64 63 62 61 60 59 58 S_VSYNC S_HSYNC S0 S1 S2 S3 S4 VDD DGND S5 S6 S7 S8 S9 CLKIN_B GND_IO PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 57 56 55 54 53 52 51 50 49 VDD_IO 1 Y0 2 48 S_BLANK Y1 3 46 VREF Y2 4 45 COMP1 Y3 5 44 DAC A Y4 6 Y5 7 Y6 8 Y7 9 PIN 1 47 RSET1 43 DAC B ADV7320/ADV7321 42 DAC C TOP VIEW (Not to Scale) 41 VAA 40 AGND VDD 10 39 DAC D DGND 11 38 DAC E Y8 12 37 DAC F Y9 13 36 COMP2 C0 14 35 RSET2 C1 15 34 EXT_LF C2 16
PAGE 18
ADV7320/ADV7321 Pin No. 62 to 58, 55 to 51 33 Mnemonic S9 to S0 Input/Output I RESET I 47, 35 RSET1, RSET2 I 22 21 20 SCLK SDA ALSB I I/O I 1 10, 56 41 46 34 31 19 64 VDD_IO VDD VAA VREF EXT_LF RTC_SCR_TR I2C GND_IO P P P I/O I I I Description SD or PS/HDTV Input Port for Cr[Red/V] Data in 4:4:4 Input Mode. LSB is set up on Pin S0. For 8-bit data input, LSB is set up on Pin S2. This input resets the on-chip timing generator and sets the ADV7320/ADV7321 into default register setting.
PAGE 19
ADV7320/ADV7321 TYPICAL PERFORMANCE CHARACTERISTICS PS Pr/Pb RESPONSE. LINEAR INTERPOLATION (4:2:2 TO 4:4:4) Y PASS BAND IN PS OVERSAMPLING MODE 1.0 0 0.5 –10 0 –0.5 –30 GAIN (dB) –40 –1.5 –50 –2.0 05067-045 –60 –70 –80 –1.0 0 20 40 60 80 100 120 140 FREQUENCY (MHz) 160 180 05067-048 GAIN (dB) –20 –2.5 –3.0 200 0 Figure 20.
PAGE 20
0 –10 –10 –20 –20 –30 –40 –30 –40 –50 –50 –60 –60 –70 05067-054 MAGNITUDE (dB) 0 05067-051 MAGNITUDE (dB) ADV7320/ADV7321 –70 0 2 4 6 8 FREQUENCY (MHz) 10 12 0 2 Figure 26. Luma NTSC Low-Pass Filter 4 6 8 FREQUENCY (MHz) 10 12 Figure 29.
PAGE 21
ADV7320/ADV7321 4 0 2 –10 MAGNITUDE (dB) –2 –4 –6 –20 –30 –40 –50 –8 –60 05067-057 –10 –70 –12 0 1 2 3 4 FREQUENCY (MHz) 5 6 05067-060 MAGNITUDE (dB) 0 7 0 Figure 32. Luma SSAF Filter—Programmable Responses 2 4 8 6 FREQUENCY (MHz) 10 12 10 12 10 12 Figure 35. Luma CIF Low-Pass Filter 5 4 –10 3 –20 MAGNITUDE (dB) MAGNITUDE (dB) 0 2 1 –30 –40 –50 –1 0 1 2 3 4 FREQUENCY (MHz) 5 6 05067-061 –60 05067-058 0 –70 0 7 Figure 33.
PAGE 22
0 –10 –10 –20 –20 –30 –40 –30 –40 –50 –50 –60 –60 –70 0 2 4 6 8 FREQUENCY (MHz) 10 05067-066 MAGNITUDE (dB) 0 05067-063 MAGNITUDE (dB) ADV7320/ADV7321 –70 12 0 0 –10 –10 –20 –20 –30 –40 –60 –60 4 6 8 FREQUENCY (MHz) 10 –70 0 12 2 4 6 8 FREQUENCY (MHz) 10 12 10 12 Figure 42. Chroma CIF Low-Pass Filter 0 –10 –10 –20 –20 –30 –40 –30 –40 –50 –50 –60 –60 –70 05067-068 MAGNITUDE (dB) 0 05067-065 MAGNITUDE (dB) Figure 39. Chroma 1.
PAGE 23
ADV7320/ADV7321 MPU PORT DESCRIPTION The ADV7320/ADV7321 support a 2-wire serial (I2Ccompatible) microprocessor bus driving multiple peripherals. This port operates in an open-drain configuration. Two inputs, serial data (SDA) and serial clock (SCL), carry information between any device connected to the bus and the ADV7320/ ADV7321. Each slave device is recognized by a unique address. The ADV7320/ADV7321 have four possible slave addresses for both read and write operations.
PAGE 24
ADV7320/ADV7321 SCLOCK S 9 1–7 8 START ADRR R/W ACK 9 1–7 8 SUBADDRESS ACK 1–7 DATA 8 9 ACK P STOP 05067-022 SDATA Figure 46. Bus Data Transfer S SLAVE ADDR A(S) SUBADDR A(S) DATA S SLAVE ADDR A(S) S = START BIT P = STOP BIT A(S) P LSB = 1 LSB = 0 READ SEQUENCE DATA A(S) SUBADDR A(S) S SLAVE ADDR A(S) = ACKNOWLEDGE BY SLAVE A(M) = ACKNOWLEDGE BY MASTER A(S) DATA A(M) A (S) = NO ACKNOWLEDGE BY SLAVE A (M) = NO ACKNOWLEDGE BY MASTER Figure 47. Read and Write Sequences Rev.
PAGE 25
ADV7320/ADV7321 REGISTER ACCESS REGISTER PROGRAMMING The MPU can write to or read from all registers of the ADV7320/ADV7321 except the subaddress registers, which are write only registers. The subaddress register selected determines which register the next read or write operation will access. All communication with the part through the bus starts with an access to the subaddress register.
PAGE 26
ADV7320/ADV7321 Table 8.
PAGE 27
ADV7320/ADV7321 Table 9. Registers 0x10 to 0x11 SR7– SR0 0x10 Register HD Mode Register 1 Bit Description HD Output Standard Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Input Sync Format HD/ED Input Mode Bit 2 Bit 1 0 0 1 Bit 0 0 1 0 1 1 0 HSYNC, VSYNC, BLANK 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 1 1 0 0 1 0 1 EAV/SAV codes SMPTE 293M, ITU-BT. 1358 Async mode BTA-1004, ITU-BT. 1362 ITU-BT. 1358 ITU-BT.
PAGE 28
ADV7320/ADV7321 Table 10.
PAGE 29
ADV7320/ADV7321 Table 12. Register 0x15 SR7– SR0 0x15 Register HD Mode Register 6 Bit Description Reserved HD RGB Input Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 1 0 1 HD Sync on PrPb 0 1 HD Color DAC Swap 0 1 HD Gamma Curve A HD Gamma Curve B HD Gamma Curve Enable 0 1 0 1 HD Adaptive Filter Mode HD Adaptive Filter Enable Bit 2 0 1 0 1 Rev. A | Page 29 of 88 Bit 0 0 Register Setting 0 must be written to this bit. Disabled. Enabled. Disabled. Enabled. DAC E = Pb; DAC F = Pr.
PAGE 30
ADV7320/ADV7321 Table 13.
PAGE 31
ADV7320/ADV7321 Table 14.
PAGE 32
ADV7320/ADV7321 Table 15. Registers 0x3E to 0x43 SR7– SR0 0x3E 0x3F 0x40 Register SD Mode Register 0 Bit Description Reserved Reserved SD Standard Bit 7 Bit 6 Bit 5 SD Luma Filter SD Chroma Filter 0x41 0x42 SD Mode Register 1 Bit 4 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 Bit 3 0 0 1 1 0 0 1 1 Bit 2 Bit 1 Bit 0 Register Setting 0 0 1 1 0 1 0 1 NTSC. PAL B, D, G, H, I. PAL M. PAL N. LPF NTSC. LPF PAL. Notch NTSC. Notch PAL. SSAF luma. Luma CIF. Luma QCIF. Reserved. 1.3 MHz. 0.
PAGE 33
ADV7320/ADV7321 Table 16. Registers 0x44 to 0x49 SR7– SR0 0x44 Register SD Mode Register 3 Bit Description SD VSYNC-3H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 SD RTC/TR/SCR SD Active Video Length Bit 1 Bit 0 0 1 Register Setting Disabled VSYNC = 2.
PAGE 34
ADV7320/ADV7321 Table 17. Registers 0x4A to 0x58 SR7– SR0 0x4A Register SD Timing Register 0 Bit Description SD Slave/Master Mode Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 SD Timing Mode SD BLANK Input SD Min. Luma Value SD Timing Reset SD Timing Register 1 x 0 1 0 0 0 1 1 0 1 0 1 0 0 0x53 0x54 0x55 0x56 0x57 0x58 0 1 0 1 0 0 0 0 0 1 1 0 1 0 1 x x 0 1 0 0 1 1 0 1 0 1 0 1 0 1 Register Setting Slave mode. Master mode. Mode 0. Mode 1. Mode 2. Mode 3. Enabled. Disabled. No delay.
PAGE 35
ADV7320/ADV7321 Table 18.
PAGE 36
ADV7320/ADV7321 Table 19.
PAGE 37
ADV7320/ADV7321 Table 20.
PAGE 38
ADV7320/ADV7321 INPUT CONFIGURATION When 10-bit input data is applied, the following bits must be set to 1: PS ONLY OR HDTV ONLY Address 0x13, Bit 2 (HD 10-bit enable) Address 0x48, Bit 4 (SD 10-bit enable) YCrCb PS, HDTV, or any other HD YCrCb data can be input in 4:2:2 or 4:4:4. In 4:2:2 input format, the Y data is input on Pins Y9 to Y0 and the CrCb data is input on Pins C9 to C0.
PAGE 39
ADV7320/ADV7321 The 8- or 10-bit SD data must be compliant with ITU-R BT.601/656 in 4:2:2 format. SD data is input on Pins S9 to S0, with S0 being the LSB. Using 8-bit input format, the data is input on Pins S9 to S2. The clock input for SD must be input on CLKIN_A, and the clock input for HD must be input on CLKIN_B. Synchronization signals are optional. SD syncs are input on Pins S_VSYNC, S_HSYNC, and S_BLANK. HD syncs are input on Pins P_VSYNC, P_HSYNC, and P_BLANK.
PAGE 40
ADV7320/ADV7321 Table 22. Input Configurations Input Format ITU-R BT.
PAGE 41
ADV7320/ADV7321 FEATURES OUTPUT CONFIGURATION Table 23, Table 24, and Table 25 demonstrate what output signals are assigned to the DACs when the control bits are set accordingly. Table 23.
PAGE 42
ADV7320/ADV7321 In async mode, the PLL must be turned off [Subaddress 0x00, Bit 1 = 1]. Register 0x10 should be programmed to 0x01. HD ASYNC TIMING MODE [Subaddress 0x10, Bits 3 and 2] Figure 58 and Figure 59 show examples of how to program the ADV7320/ADV7321 to accept a high definition standard other than SMPTE 293M, SMPTE 274M, SMPTE 296M, or ITU-R BT.1358.
PAGE 43
ADV7320/ADV7321 b. HD TIMING RESET A timing reset is achieved by toggling the HD timing reset control bit [Subaddress 0x14, Bit 0] from 0 to 1. In this state, the horizontal and vertical counters remain reset. When this bit is set back to 0, the internal counters resume counting. This reset signal must be held high for a minimum of one clock cycle. The minimum time the pin must be held high is one clock cycle; otherwise, this reset signal might not be recognized.
PAGE 44
ADV7320/ADV7321 DISPLAY 307 START OF FIELD 4 OR 8 310 FSC PHASE = FIELD 4 OR 8 313 320 NO FSC RESET APPLIED 307 START OF FIELD 4 OR 8 310 FSC PHASE = FIELD 1 313 320 FSC RESET PULSE FSC RESET APPLIED 05067-037 DISPLAY Figure 61.
PAGE 45
ADV7320/ADV7321 In fast forward mode, the sync information at the start of a new field in the incoming video usually occurs before the correct number of lines/fields are reached; in rewind mode, this sync signal usually occurs after the total number of lines/fields are reached. Conventionally this means that the output video will have corrupted field signals because one signal is generated by the incoming video and another is generated when the internal lines/field counters reach the end of a field.
PAGE 46
ADV7320/ADV7321 VERTICAL BLANKING INTERVAL SUBCARRIER FREQUENCY REGISTERS The ADV7320/ADV7321 accepts input data that contains VBI data (such as CGMS, WSS, VITS) in SD and HD modes. [Subaddresses 0x4C to 0x4F] For the SMPTE 293M (525p) standard, VBI data can be inserted on Lines 13 to 42 of each frame, or on Lines 6 to 43 for the ITU-R BT.1358 (625p) standard. Four 8-bit registers are used to set up the subcarrier frequency.
PAGE 47
ADV7320/ADV7321 SQUARE PIXEL TIMING MODE [Address 0x42, Bit 4] In square pixel mode, the following timing diagrams apply.
PAGE 48
ADV7320/ADV7321 EXTENDED UV FILTER MODE FILTERS 0 Table 27 shows an overview of the programmable filters available on the ADV7320/ADV7321. –10 Table 27. Selectable Filters Subaddress 0x40 0x40 0x40 0x40 0x40 0x40 0x40 0x40 0x40 0x40 0x40 0x40 0x40 0x40 0x42 0x13 0x13 0x13 GAIN (dB) –20 –30 –40 –50 05067-044 Filter SD Luma LPF NTSC SD Luma LPF PAL SD Luma Notch NTSC SD Luma Notch PAL SD Luma SSAF SD Luma CIF SD Luma QCIF SD Chroma 0.65 MHz SD Chroma 1.0 MHz SD Chroma 1.3 MHz SD Chroma 2.
PAGE 49
ADV7320/ADV7321 Table 29. Sample Color Values for EIA 770.2 Output Standard Selection PS/HD Sinc Filter [Subaddress 0x13, Bit 3] Sample Color White Black Red Green Blue Yellow Cyan Magenta 0.5 0.4 0.3 GAIN (dB) 0.2 0.1 0 –0.1 –0.2 Y Value 235 (EB) 16 (10) 81 (51) 145 (91) 41 (29) 210 (D2) 170 (AA) 106 (6A) Cr Value 128 (80) 128 (80) 240 (F0) 34 (22) 110 (6E) 146 (92) 16 (10) 222 (DE) Cb Value 128 (80) 128 (80) 90 (5A) 54 (36) 240 (F0) 16 (10) 166 (A6) 202 (CA) RGB Matrix –0.
PAGE 50
ADV7320/ADV7321 This is reflected in the preprogrammed values for GY = 0x13B, GU = 0x3B, GV = 0x93, BU = 0x248, and RV = 0x1F0. Upon power-up, the RGB matrix is programmed with the default values listed in Table 31. If the RGB matrix is enabled and another input standard (such as SD or PS) is used, the scale values for GY, GU, GV, BU, and RV must be adjusted according to this input standard color space. The user should consider that the color component conversion might use different scale values.
PAGE 51
ADV7320/ADV7321 SD Hue Adjust Value For example, [Subaddress 0x60] The hue adjust value is used to adjust the hue on the composite and chroma outputs. These eight bits represent the value required to vary the hue of the video data, that is, the variance in phase of the subcarrier during active video with respect to the phase of the subcarrier during the color burst. The ADV7320/ADV7321 provide a range of ±22.5° increments of 0.17578125°.
PAGE 52
ADV7320/ADV7321 Double buffering can be activated on the following HD registers: HD Gamma Curve A, HD Gamma Curve B, and HD CGMS registers. SD Brightness Detect [Subaddress 0x7A] The ADV7320/ADV7321 allow monitoring the brightness level of the incoming video data. Brightness detect is a read-only register.
PAGE 53
ADV7320/ADV7321 Table 33. DAC Gain Control PROGRAMMABLE DAC GAIN CONTROL Reg 0x0A or 0x0B 0100 0000 (0x40) 0011 1111 (0x3F) 0011 1110 (0x3E) ... ... 0000 0010 (0x02) 0000 0001 (0x01) 0000 0000 (0x00) DAC Current (mA) 4.658 4.653 4.648 ... ... 4.43 4.38 4.33 % Gain 7.5000% 7.3820% 7.3640% ... ... 0.0360% 0.0180% 0.0000% 1111 1111 (0xFF) 1111 1110 (0xFE) ... ... 1100 0010 (0xC2) 1100 0001 (0xC1) 1100 0000 (0xC0) 4.25 4.23 ... ... 4.018 4.013 4.008 −0.0180% −0.0360% ... ... −7.3640% −7.3820% −7.
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ADV7320/ADV7321 For lengths of 16 to 240 points, the gamma correction curve is calculated as follows: ⎡ x ⎤ yn = ⎢ (n −16) ⎥ γ × (240 − 16) + 16 ⎣ (240 − 16) ⎦ SIGNAL OUTPUT 200 0.5 150 100 SIGNAL INPUT 50 0 For example, y24 = [(8/224)0.5 × 224] + 16 = 58 y32 = [(16/224)0.5 × 224] + 16 = 76 y48 = [(32/224)0.5 × 224] + 16 = 101 y64 = [(48/224)0.5 × 224] + 16 = 120 y80 = [(64/224)0.5 × 224] + 16 = 136 y128 = [(112/224)0.
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ADV7320/ADV7321 The derivative of the incoming signal is compared to the three programmable threshold values: HD Adaptive Filter Threshold A, B, and C. The recommended threshold range is from 16 to 235, but any value between 0 and 255 can be used. HD SHARPNESS FILTER AND ADAPTIVE FILTER CONTROLS [Subaddresses 0x20, 0x38 to 0x3D] There are three filter modes available on the ADV7320/ADV7321: sharpness filter mode and two adaptive filter modes.
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ADV7320/ADV7321 HD SHARPNESS FILTER AND ADAPTIVE FILTER APPLICATION EXAMPLES HD Sharpness Filter Application The HD sharpness filter can be used to enhance or attenuate the Y video output signal. The register settings listed in Table 34 were used to achieve the results shown in Figure 74. Input data was generated by an external signal source. Table 34. Sharpness Control Address 0x00 0x01 0x02 0x10 0x11 0x20 0x20 0x20 0x20 0x20 0x20 Reference 1 a b c d e f See Figure 74.
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ADV7320/ADV7321 Adaptive Filter Control Application 05067-075 05067-077 Figure 75 and Figure 76 show how a typical signal is processed by the adaptive filter control block in Mode A. When changing the adaptive filter mode to Mode B [Address 0x15, Bit 6], the output shown in Figure 77 can be obtained from the input signal shown in Figure 75. Figure 77. Output Signal with Adaptive Filter Control (Mode B) Figure 75.
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ADV7320/ADV7321 In DNR sharpness mode, the range of gain values is 0 to 0.5 in increments of 1/16. This factor is applied to the DNR filter output, which lies above the threshold range. The result is added to the original signal.
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ADV7320/ADV7321 original signal, since this data is assumed to be valid data and not noise. The overall effect is that the signal is boosted (similar to using an extended SSAF filter). 1.0 FILTER D BLOCK OFFSET CONTROL FILTER C [Address 0x65, Bits 7 to 4] 0.6 0.4 Four bits are assigned to this control, which allows a maximum shift of 15 pixels in a data block. Consider the fixed coring gain positions.
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ADV7320/ADV7321 VOLTS IRE:FLT 100 0.5 50 0 F2 L135 –50 0 2 4 6 8 10 12 05067-083 0 Figure 83. Address 0x42, Bit 7 = 0 VOLTS IRE:FLT 100 0.5 50 0 F2 L135 –50 –2 0 2 4 6 8 Figure 84. Address 0x42, Bit 7 = 1 Rev.
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ADV7320/ADV7321 HSYNC/VSYNC OUTPUT CONTROL The ADV7320/ADV7321 have the ability to accept either embedded time codes in the input data, or external Hsync and Vsync signals on P_HSYNC/P_VSYNC, outputting the respective signals on the S_HSYNC and S_VSYNC pins. Table 36.
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ADV7320/ADV7321 BOARD DESIGN AND LAYOUT CIRCUIT FREQUENCY RESPONSE 0 0 24n –30 –10 The ADV7320/ADV7321 contain an on-board voltage reference. The ADV7320/ADV7321 can be used with an external VREF (AD1580). –60 18n –90 GAIN (dB) –30 15n –120 –40 9n –180 GROUP DELAY (Seconds) –60 6n –210 –70 VIDEO OUTPUT BUFFER AND OPTIONAL OUTPUT FILTER –80 1M Output buffering on all six DACs is necessary to drive output devices, such as SD or HD monitors.
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ADV7320/ADV7321 CIRCUIT FREQUENCY RESPONSE 0 480 18n 400 –10 MAGNITUDE (dB) 16n 320 –20 14n 240 GAIN (dB) –30 PHASE (Degrees) GROUP DELAY (Seconds) –40 12n 160 10n –50 80 –60 0 8n –70 –80 –80 –160 10M 100M FREQUENCY (Hz) 05067-089 4n 2n –240 0 1G Figure 89.
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ADV7320/ADV7321 Analog Signal Interconnect Locate the ADV7320/ADV7321 as close as possible to the output connectors to minimize noise pickup and reflections due to impedance mismatch. For optimum performance, each analog output should be source- and load-terminated, as shown in Figure 91. The termination resistors should be as close as possible to the ADV7320/ADV7321 to minimize reflections.
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ADV7320/ADV7321 APPENDIX 1—COPY GENERATION MANAGEMENT SYSTEM PS CGMS SD CGMS Data Registers 2 to 0 Data Registers 2 to 0 [Subaddresses 0x21, 0x22, 0x23] [Subaddresses 0x59, 0x5A, 0x5B] 525p The ADV7320/ADV7321 support copy generation management system (CGMS), conforming to the EIAJ CPR-1204 and ARIB TR-B15 standards. CGMS data is transmitted on Line 20 for odd fields and Line 283 for even fields. Bits C/W05 and C/W06 control whether CGMS data is output on odd or even fields.
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ADV7320/ADV7321 CRC SEQUENCE +700mV REF 70% ± 10% C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 0mV –300mV T = 1/(fH × 33) = 963ns fH = HORIZONTAL SCAN FREQUENCY T ± 30ns Figure 92. PS 525p CGMS Waveform (Line 41) R = RUN-IN S = START CODE PEAK WHITE 500mV ± 25mV R S C0 C1 LSB SYNC LEVEL C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 MSB 05067-093 13.7μs 5.5μs ± 0.125μs Figure 93.
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ADV7320/ADV7321 CRC SEQUENCE +700mV REF 70% ± 10% C0 C1 0mV C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 T ± 30ns 17.2μs ± 160ns 22T T = 1/(fH × 1650/58) = 781.93ns fH = HORIZONTAL SCAN FREQUENCY 1H 4T 3.128μs ± 90ns 05067-095 –300mV C2 Figure 95. HDTV 720p CGMS Waveform CRC SEQUENCE +700mV REF 70% ± 10% C0 0mV C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 T ± 30ns 4T 4.15μs ± 60ns 22.84μs ± 210ns 22T T = 1/(fH × 2200/77) = 1.
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ADV7320/ADV7321 APPENDIX 2—SD WIDE SCREEN SIGNALING preceded by a run-in sequence and a start code (see Figure 97). If SD WSS [Address 0x59, Bit 7] is set to Logic 1, it enables the WSS data to be transmitted on Line 23. The latter portion of Line 23 (42.5 sec after the falling edge of HSYNC) is available for the insertion of video. It is possible to blank the WSS portion of Line 23 with Subaddress 0x61, Bit 7.
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ADV7320/ADV7321 APPENDIX 3—SD CLOSED CAPTIONING FCC Code of Federal Regulations (CFR) 47 section 15.119 and EIA608 describe the closed captioning information for Line 21 and Line 284. [Subaddresses 0x51 to 0x54] The ADV7320/ADV7321 support closed captioning conforming to the standard television synchronizing waveform for color transmission. Closed captioning is transmitted during the blanked active line time of Line 21 of the odd fields and Line 284 of the even fields.
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ADV7320/ADV7321 APPENDIX 4—TEST PATTERNS The ADV7320/ADV7321 can generate SD and HD test patterns. T 05067-099 2 CH2 200mV M 10.0μs A CH2 30.6000μs T 05067-102 T 2 CH2 100mV 1.20V Figure 99. NTSC Color Bars M 10.0μs CH2 1.82600ms T EVEN Figure 102. PAL Black Bar (–21 mV, 0 mV, 3.5 mV, 7 mV, 10.5 mV, 14 mV, 18 mV, 23 mV) T 05067-100 2 CH2 200mV M 10.0μs A CH2 30.6000μs T 05067-103 T 2 CH2 200mV 1.21V M 4.0μs CH2 1.82944ms T EVEN Figure 103. 525p Hatch Pattern Figure 100.
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ADV7320/ADV7321 05067-105 2 CH2 200mV M 4.0μs CH2 1.82872ms T 05067-107 T T 2 CH2 100mV EVEN M 4.0μs CH2 1.82936ms T EVEN Figure 107. 525p Black Bar (−35 mV, 0 mV, 7 mV, 14 mV, 21 mV, 28 mV, 35 mV) Figure 105. 525p Field Pattern 05067-106 2 CH2 200mV M 4.0μs CH2 1.84176ms T 05067-108 T T 2 CH2 100mV EVEN M 4.0μs CH2 1.84176ms T EVEN Figure 108. 625p Black Bar (−35 mV, 0 mV, 7 mV, 14 mV, 21 mV, 28 mV, 5 mV) Figure 106. 625p Field Pattern Rev.
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ADV7320/ADV7321 The register settings in Table 41 are used to generate an SD NTSC CVBS output on DAC A, S-video on DACs B and C, and YPrPb on DACs D, E, and F. Upon power-up, the subcarrier registers are programmed with the appropriate values for NTSC. All other registers are set as normal/default. Table 41.
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ADV7320/ADV7321 APPENDIX 5—SD TIMING MODES [Subaddress 0x4A] MODE 0 (CCIR-656)—SLAVE OPTION (TIMING REGISTER 0 TR0 = X X X X X 0 0 0) The ADV7320/ADV7321 are controlled by the SAV (start active video) and EAV (end active video) time codes in the pixel data. All timing information is transmitted using a 4-byte synchronization pattern. A synchronization pattern is sent immediately before and after each line during active picture and retrace.
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ADV7320/ADV7321 MODE 0 (CCIR-656)—MASTER OPTION (TIMING REGISTER 0 TR0 = X X X X X 0 0 1) The ADV7320/ADV7321 generate H, V, and F signals required for the SAV (start active video) and EAV (end active video) time codes in the CCIR656 standard. The H, V, and F bits are output on S_HSYNC, S_BLANK, and S_VSYNC, respectively.
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ADV7320/ADV7321 DISPLAY DISPLAY VERTICAL BLANK 622 623 624 625 1 2 3 4 5 6 21 7 22 23 H V EVEN FIELD F ODD FIELD DISPLAY DISPLAY VERTICAL BLANK 309 310 311 312 313 314 315 316 317 318 319 320 334 335 336 H ODD FIELD F 05067-111 V EVEN FIELD Figure 111. SD Master Mode 0 (PAL) ANALOG VIDEO H 05067-112 F V Figure 112. SD Master Mode 0 (Data Transitions) Rev.
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ADV7320/ADV7321 MODE 1—SLAVE OPTION (TIMING REGISTER 0 TR0 = X X X X X 0 1 0) In this mode, the ADV7320/ADV7321 accept horizontal sync and odd/even field signals. When HSYNC is low, a transition of the field input indicates a new frame, that is, vertical retrace. The BLANK signal is optional. When the BLANK input is disabled, ADV7320/ADV7321 automatically blank all normally blank lines as per CCIR-624. HSYNC, BLANK, and FIELD are input on S_HSYNC, S_BLANK, and S_VSYNC, respectively.
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ADV7320/ADV7321 MODE 1—MASTER OPTION (TIMING REGISTER 0 TR0 = X X X X X 0 1 1) In this mode, the ADV7320/ADV7321 can generate horizontal sync and odd/even field signals. When HSYNC is low, a transition of the field input indicates a new frame, that is, vertical retrace. The BLANK signal is optional. When the BLANK input is disabled, ADV7320/ADV7321 automatically blank all normally blank lines as per CCIR-624. Pixel data is latched on the rising clock edge following the timing signal transitions.
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ADV7320/ADV7321 MODE 2— SLAVE OPTION (TIMING REGISTER 0 TR0 = X X X X X 1 0 0) In this mode, the ADV7320/ADV7321 accept horizontal and vertical sync signals. A coincident low transition of both HSYNC and VSYNC inputs indicates the start of an odd field. A VSYNC low transition when HSYNC is high indicates the start of an even field. The BLANK signal is optional. When the BLANK input is disabled, ADV7320/ADV7321 automatically blank all normally blank lines as per CCIR-624.
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ADV7320/ADV7321 MODE 2—MASTER OPTION (TIMING REGISTER 0 TR0 = X X X X X 1 0 1) In this mode, the ADV7320/ADV7321 can generate horizontal and vertical sync signals. A coincident low transition of both HSYNC and VSYNC inputs indicates the start of an odd field. A VSYNC low transition when HSYNC is high indicates the start of an even field. The BLANK signal is optional. When the BLANK input is disabled, the ADV7320/ADV7321 automatically blank all normally blank lines as per CCIR-624.
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ADV7320/ADV7321 MODE 3—MASTER/SLAVE OPTION (TIMING REGISTER 0 TR0 = X X X X X 1 1 0 OR X X X X X 1 1 1) In this mode, the ADV7320/ADV7321 accept or generate horizontal sync and odd/even field signals. When HSYNC is high, a transition of the field input indicates a new frame, that is, vertical retrace. The BLANK signal is optional. When the BLANK input is disabled, ADV7320/ADV7321 automatically blank all normally blank lines as per CCIR-624.
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ADV7320/ADV7321 APPENDIX 6—HD TIMING DISPLAY FIELD 1 VERTICAL BLANKING INTERVAL 1124 1125 1 2 3 4 5 6 7 8 20 21 22 560 P_VSYNC P_HSYNC DISPLAY VERTICAL BLANKING INTERVAL FIELD 2 561 562 563 564 565 566 567 568 569 570 583 584 585 1123 05067-122 P_VSYNC P_HSYNC Figure 122. 1080i HSYNC and VSYNC Input Timing Rev.
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ADV7320/ADV7321 APPENDIX 7—VIDEO OUTPUT LEVELS HD YPrPb OUTPUT LEVELS INPUT CODE EIA-770.2, STANDARD FOR Y OUTPUT VOLTAGE INPUT CODE EIA-770.3, STANDARD FOR Y OUTPUT VOLTAGE 940 940 700mV 700mV 64 64 300mV 300mV EIA-770.2, STANDARD FOR Pr/Pb EIA-770.3, STANDARD FOR Pr/Pb OUTPUT VOLTAGE 960 OUTPUT VOLTAGE 960 600mV 700mV 512 512 64 64 Figure 123. EIA 770.2 Standard Output Signals (525p/625p) INPUT CODE EIA-770.1, STANDARD FOR Y 05067-125 05067-123 700mV Figure 125. EIA 770.
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ADV7320/ADV7321 RGB OUTPUT LEVELS Pattern: 100%/75% Color Bars 700mV 525mV 700mV 300mV 300mV 700mV 525mV 300mV 700mV 525mV 700mV 525mV 05067-127 525mV 300mV Figure 127. PS RGB Output Levels 700mV Figure 129. SD RGB Output Levels—RGB Sync Disabled 700mV 525mV 300mV 300mV 0mV 0mV 700mV 525mV 300mV 300mV 0mV 0mV 700mV 525mV 525mV 700mV 525mV 700mV 525mV 300mV 05067-128 300mV 0mV Figure 128.
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05067-136 05067-133 Figure 133. Pr Levels—NTSC Rev. A | Page 84 of 88 Figure 135. Y Levels—NTSC Figure 136. Y Levels—PAL RED MAGENTA GREEN CYAN YELLOW WHITE BLACK 05067-135 300mV BLACK 700mV BLUE 700mV BLUE RED MAGENTA GREEN Figure 132. Pb Levels—PAL CYAN 05067-132 BLACK BLUE RED MAGENTA GREEN CYAN YELLOW WHITE Figure 131.
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ADV7320/ADV7321 VOLTS VOLTS IRE:FLT 0.6 100 0.4 0.5 50 0.2 0 0 10 0 20 30 40 MICROSECONDS 50 05067-140 F1 L76 –50 –0.2 05067-137 0 L608 0 20 30 40 50 60 MICROSECONDS PRECISION MODE OFF NOISE REDUCTION: 0.00dB APL = 39.1% SYNCHRONOUS SOUND-IN-SYNC OFF 625 LINE NTSC NO FILTERING FRAMES SELECTED 1, 2, 3, 4 SLOW CLAMP TO 0.00 AT 6.72μs 60 PRECISION MODE OFF APL = 44.5% SYNCHRONOUS SYNC = A 525 LINE NTSC FRAMES SELECTED 1, 2 SLOW CLAMP TO 0.00V AT 6.72μs 10 Figure 137.
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ADV7320/ADV7321 APPENDIX 8—VIDEO STANDARDS 0HDATUM SMPTE 274M ANALOG WAVEFORM DIGITAL HORIZONTAL BLANKING *1 272T 4T EAV CODE F F INPUT PIXELS ANCILLARY DATA (OPTIONAL) OR BLANKING CODE 4T 1920T SAV CODE DIGITAL ACTIVE LINE F 0 0 F C V b Y C r F 0 0 H* 0 0 F 0 0 V H* 4 CLOCK SAMPLE NUMBER 2112 C Y r 4 CLOCK 0 2199 2116 2156 44 188 192 2111 05067-143 FVH* = FVH AND PARITY BITS SAV/EAV: LINE 1–562: F = 0 SAV/EAV: LINE 563–1125: F = 1 SAV/EAV: LINE 1–20; 561–583; 1124–1125: V = 1 SAV/EAV:
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ADV7320/ADV7321 522 523 ACTIVE VIDEO VERTICAL BLANK 524 525 1 2 5 6 7 8 9 12 13 14 15 16 42 43 05067-145 ACTIVE VIDEO 44 Figure 145. SMPTE 293M (525p) 622 623 ACTIVE VIDEO VERTICAL BLANK 624 625 1 2 5 4 6 7 8 9 10 11 12 13 43 44 45 05067-146 ACTIVE VIDEO Figure 146. ITU-R BT.1358 (625p) DISPLAY 747 748 749 1 750 4 3 2 6 5 7 8 25 26 27 744 745 05067-147 VERTICAL BLANKING INTERVAL Figure 147.
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ADV7320/ADV7321 OUTLINE DIMENSIONS 0.75 0.60 0.45 12.00 BSC SQ 1.60 MAX 64 49 1 48 PIN 1 10.00 BSC SQ TOP VIEW (PINS DOWN) 1.45 1.40 1.35 0.15 0.05 0.20 0.09 7° 3.5° 0° 0.08 MAX COPLANARITY SEATING PLANE VIEW A 16 33 32 17 VIEW A 0.50 BSC LEAD PITCH 0.27 0.22 0.17 ROTATED 90° CCW COMPLIANT TO JEDEC STANDARDS MS-026-BCD Figure 149.