Data Sheet FEATURES 74.25 MHz 16-/24-bit high definition input support Compliant with SMPTE 274M (1080i), 296M (720p), and 240M (1035i) Six 11-bit, 297 MHz video DACs 16× (216 MHz) DAC oversampling for SD 8× (216 MHz) DAC oversampling for ED 4× (297 MHz) DAC oversampling for HD 37 mA maximum DAC output current NTSC M, PAL B/D/G/H/I/M/N, PAL 60 support NTSC and PAL square pixel operation (24.54 MHz/29.
ADV7342/ADV7343 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 SD Subcarrier Frequency Lock ................................................. 53 Applications ....................................................................................... 1 SD VCR FF/RW Sync ................................................................ 54 Revision History ...................................................................
Data Sheet ADV7342/ADV7343 HD CGMS ....................................................................................76 ED/HD YPrPb Output Levels ................................................... 89 CGMS CRC Functionality .........................................................76 SD/ED/HD RGB Output Levels ................................................ 90 SD Wide Screen Signaling ..............................................................79 SD Output Plots ..................................
ADV7342/ADV7343 Data Sheet REVISION HISTORY 3/12—Rev. C to Rev. D Changed ADV7340/ADV7341 to ADV7342/ADV7343 ........... 70 3/12—Rev. B to Rev. C Reorganized Layout ............................................................ Universal Change to Features Section ............................................................. 1 Moved Revision History Section .................................................... 4 Change to Table 1 .............................................................................
Data Sheet ADV7342/ADV7343 GENERAL DESCRIPTION The ADV7342/ADV7343 are high speed, digital-to-analog video encoders in a 64-lead LQFP package. Six high speed, 3.3 V, 11-bit video DACs provide support for composite (CVBS), S-Video (Y-C), and component (YPrPb/RGB) analog outputs in standard definition (SD), enhanced definition (ED), or high definition (HD) video formats. The ADV7342/ADV7343 have a 24-bit pixel input port that can be configured in a variety of ways.
ADV7342/ADV7343 Data Sheet FUNCTIONAL BLOCK DIAGRAM SCL SDA ALSB VIDEO DATA 4:2:2 TO 4:4:4 SD DEINTERLEAVE R G/B 8-/16-/24-BIT ED/HD SUBCARRIER FREQUENCY LOCK (SFL) MPU PORT VIDEO DATA RGB TO YCrCb MATRIX RGB ASYNC BYPASS POWER MANAGEMENT CONTROL ADD SYNC PROGRAMMABLE LUMINANCE FILTER ADD BURST PROGRAMMABLE CHROMINANCE FILTER YCrCb TO RGB SIN/COS DDS BLOCK 16× FILTER 16× FILTER RGB YCbCr SDR/DDR ED/HD INPUT 4:2:2 TO 4:4:4 DEINTERLEAVE VAA ADV7342/ADV7343 VBI DATA SERVICE INSERTION
Data Sheet ADV7342/ADV7343 SPECIFICATIONS POWER SUPPLY AND VOLTAGE SPECIFICATIONS All specifications TMIN to TMAX (−40°C to +85°C), unless otherwise noted. Table 2. Parameter SUPPLY VOLTAGES VDD VDD_IO PVDD VAA POWER SUPPLY REJECTION RATIO Min Typ Max Unit 1.71 1.71 1.71 2.6 1.8 3.3 1.8 3.3 0.002 1.89 3.63 1.89 3.465 V V V V %/% Min 1.186 1.15 Typ 1.248 1.235 ±10 Max 1.31 1.
ADV7342/ADV7343 Data Sheet ANALOG OUTPUT SPECIFICATIONS VDD = 1.71 V to 1.89 V, PVDD = 1.71 V to 1.89 V, VAA = 2.6 V to 3.465 V, VDD_IO = 1.71 V to 3.63 V VREF = 1.235 V (driven externally). All specifications TMIN to TMAX (−40°C to +85°C), unless otherwise noted. Table 5.
Data Sheet ADV7342/ADV7343 DIGITAL TIMING SPECIFICATIONS—3.3 V VDD = 1.71 V to 1.89 V, PVDD = 1.71 V to 1.89 V, VAA = 2.6 V to 3.465 V, VDD_IO = 2.97 V to 3.63 V. All specifications TMIN to TMAX (−40°C to +85°C), unless otherwise noted. Table 8.
ADV7342/ADV7343 Data Sheet DIGITAL TIMING SPECIFICATIONS—1.8 V VDD = 1.71 V to 1.89 V, PVDD = 1.71 V to 1.89 V, VAA = 2.6 V to 3.465 V, VDD_IO = 1.71 V to 1.89 V. All specifications TMIN to TMAX (−40°C to +85°C), unless otherwise noted. Table 9.
Data Sheet ADV7342/ADV7343 MPU PORT TIMING SPECIFICATIONS VDD = 1.71 V to 1.89 V, PVDD = 1.71 V to 1.89 V, VAA = 2.6 V to 3.465 V, VDD_IO = 1.71 V to 3.63 V. All specifications TMIN to TMAX (−40°C to +85°C), unless otherwise noted. Table 10.
ADV7342/ADV7343 Data Sheet VIDEO PERFORMANCE SPECIFICATIONS VDD = 1.8 V, PVDD = 1.8 V, VAA = 3.3 V, VDD_IO = 3.3 V, TA = 25°C, VREF driven externally. Table 12. Parameter STATIC PERFORMANCE Resolution Integral Nonlinearity Differential Nonlinearity 1 +ve Differential Nonlinearity1 −ve STANDARD DEFINTION (SD) MODE Luminance Nonlinearity Differential Gain Differential Phase Signal-to-Noise Ratio (SNR) Conditions Typ Max Unit RSET1 = 510 kΩ, RL1 = 37.5 Ω RSET2 = 4.
Data Sheet ADV7342/ADV7343 TIMING DIAGRAMS The following abbreviations are used in Figure 2 to Figure 13: t9 = clock high time t10 = clock low time t11 = data setup time t12 = data hold time t13 = control output access time t14 = control output hold time In addition, refer to Table 36 for the ADV7342/ADV7343 input configuration.
ADV7342/ADV7343 Data Sheet CLKIN_A t9 CONTROL INPUTS t12 t10 P_HSYNC, P_VSYNC, P_BLANK Y7 TO Y0 Y0 Y1 Y2 Y3 Y4 Y5 C7 TO C0 Cb0 Cr0 Cb2 Cr2 Cb4 Cr4 t11 t13 06399-005 CONTROL OUTPUTS t14 Figure 5.
Data Sheet ADV7342/ADV7343 CLKIN_A* t9 CONTROL INPUTS t10 P_HSYNC, P_VSYNC, P_BLANK Y7 TO Y0 Cb0 t11 Y0 Cr0 Cb2 Y1 Y2 Cr2 t12 t12 t11 t13 CONTROL OUTPUTS 06399-008 t14 *LUMA/CHROMA CLOCK RELATIONSHIP CAN BE INVERTED USING SUBADDRESS 0x01, BITS 1 AND 2. Figure 8.
ADV7342/ADV7343 Data Sheet CLKIN_B CONTROL INPUTS t9 P_HSYNC, P_VSYNC, P_BLANK t10 EH/HD INPUT Y0 Cb0 Y7 TO Y0 t11 Cr0 Y1 t12 Cb2 Y2 Cr2 t12 t11 CLKIN_A t9 CONTROL INPUTS t12 t10 S_HSYNC, S_VSYNC SD INPUT Cb0 Cr0 Y0 Y1 Cb2 Y2 Cr2 06399-011 S7 TO S0 t11 Figure 11.
Data Sheet ADV7342/ADV7343 Y OUTPUT c P_HSYNC P_VSYNC a P_BLANK Y7 TO Y0 Y0 Y1 Y2 Y3 C7 TO C0 Cb0 Cr0 Cb2 Cr2 b a AND b AS PER RELEVANT STANDARD. 06399-014 c = PIPELINE DELAY. PLEASE REFER TO RELEVANT PIPELINE DELAY. THIS CAN BE FOUND IN THE DIGITAL TIMING SPECIFICATION SECTION OF THE DATA SHEET. A FALLING EDGE OF HSYNC INTO THE ENCODER GENERATES A SYNC FALLING EDGE ON THE OUTPUT AFTER A TIME EQUAL TO THE PIPELINE DELAY. Figure 14.
ADV7342/ADV7343 Data Sheet Y OUTPUT c P_HSYNC P_VSYNC a P_BLANK Y7 TO Y0 Y0 Y1 Y2 Y3 C7 TO C0 Cb0 Cr0 Cb2 Cr2 b a AND b AS PER RELEVANT STANDARD. 06399-016 c = PIPELINE DELAY. PLEASE REFER TO RELEVANT PIPELINE DELAY. THIS CAN BE FOUND IN THE DIGITAL TIMING SPECIFICATION SECTION OF THE DATA SHEET. A FALLING EDGE OF HSYNC INTO THE ENCODER GENERATES A FALLING EDGE OF TRI-LEVEL SYNC ON THE OUTPUT AFTER A TIME EQUAL TO THE PIPELINE DELAY. Figure 16.
Data Sheet ADV7342/ADV7343 S_HSYNC S_VSYNC Cb Cr Y PAL = 264 CLOCK CYCLES NTSC = 244 CLOCK CYCLES *SELECTED BY SUBADDRESS 0x01, BIT 7. Figure 18. SD Input Timing Diagram (Timing Mode 1) t3 t5 t3 SDA t1 t2 t7 t4 t8 2 Figure 19. MPU Port Timing Diagram (I C Mode) Rev.
ADV7342/ADV7343 Data Sheet ABSOLUTE MAXIMUM RATINGS Table 13. Parameter1 VAA to AGND VDD to DGND PVDD to PGND VDD_IO to GND_IO AGND to DGND AGND to PGND AGND to GND_IO DGND to PGND DGND to GND_IO PGND to GND_IO Digital Input Voltage to GND_IO Analog Outputs to AGND Maximum CLKIN Input Frequency Storage Temperature Range (TS) Junction Temperature (TJ) Lead Temperature (Soldering, 10 sec) 1 Rating −0.3 V to +3.9 V −0.3 V to +2.3 V −0.3 V to +2.3 V −0.3 V to +3.9 V −0.3 V to +0.3 V −0.3 V to +0.3 V −0.
Data Sheet ADV7342/ADV7343 64 63 62 61 60 59 58 S_VSYNC S_HSYNC TEST4 TEST5 S0 S1 S2 VDD DGND S3 S4 S5 S6 S7 CLKIN_B GND_IO PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 57 56 55 54 53 52 51 50 49 VDD_IO 1 TEST0 2 TEST1 3 46 VREF Y0 4 45 COMP1 Y1 5 44 DAC 1 Y2 6 43 DAC 2 Y3 7 Y4 8 Y5 9 PIN 1 ADV7342/ADV7343 TOP VIEW (Not to Scale) 48 SFL 47 RSET1 42 DAC 3 41 VAA 40 AGND VDD 10 39 DAC 4 DGND 11 38 DAC 5 DAC 6 Y6 12 37 Y7 13 36 RSET2 TEST2 14
ADV7342/ADV7343 Data Sheet 36 RSET2 I 45, 35 O O DAC Outputs. Full- and low-drive capable DACs. O DAC Outputs. Low-drive only capable DACs. 21 20 19 COMP1, COMP2 DAC 1, DAC 2, DAC 3 DAC 4, DAC 5, DAC 6 SCL SDA ALSB This pin is used to control the amplitudes of the DAC 4, DAC 5, and DAC 6 outputs. A 4.12 kΩ resistor must be connected from RSET2 to AGND. Compensation Pins. Connect a 2.2 nF capacitor from both COMP pins to VAA.
Data Sheet ADV7342/ADV7343 TYPICAL PERFORMANCE CHARACTERISTICS ED Pr/Pb RESPONSE. LINEAR INTERP FROM 4:2:2 TO 4:4:4 Y RESPONSE IN ED 8× OVERSAMPLING MODE 1.0 0 0.5 –10 0 –0.5 –30 GAIN (dB) –40 –1.0 –1.5 –50 –60 –2.0 –70 –2.5 0 20 40 60 80 100 120 140 FREQUENCY (MHz) 160 180 200 –3.0 06399-022 –80 Figure 21. ED 8× Oversampling, PrPb Filter (Linear) Response 0 2 4 6 8 FREQUENCY (MHz) 10 06399-025 GAIN (dB) –20 12 Figure 24.
ADV7342/ADV7343 Data Sheet Y RESPONSE IN HD 4× OVERSAMPLING MODE 10 0 0 –10 –10 MAGNITUDE (dB) –20 GAIN (dB) –30 –40 –50 –60 –20 –30 –40 –50 –70 –80 –60 –90 37.0 55.5 74.0 92.5 FREQUENCY (MHz) 111.0 129.5 148.0 –70 0 2 4 6 8 FREQUENCY (MHz) 10 12 06399-031 18.5 12 06399-032 0 06399-028 –100 Figure 30. SD PAL, Luma Low-Pass Filter Response Figure 27. HD 4× Oversampling, Y Filter Response Y PASS BAND IN HD 4x OVERSAMPLING MODE 3.0 0 0 –10 –1.
Data Sheet ADV7342/ADV7343 Y RESPONSE IN SD OVERSAMPLING MODE 5 0 4 –10 MAGNITUDE (dB) GAIN (dB) –20 –30 –40 –50 3 2 1 –60 0 0 20 40 60 80 100 120 140 FREQUENCY (MHz) 160 180 –1 06399-034 –80 200 0 Figure 33. SD, 16× Oversampling, Y Filter Response 3 4 FREQUENCY (MHz) 2 1 5 6 7 06399-037 –70 Figure 36.
Data Sheet 0 –10 –10 –20 –20 –30 –40 –50 –60 –60 4 8 6 FREQUENCY (MHz) 10 12 –70 0 Figure 39. SD Luma QCIF Low-Pass Filter Response –10 –10 –20 –20 MAGNITUDE (dB) 0 –30 –40 –60 –60 10 12 0 2 4 8 6 FREQUENCY (MHz) 10 Figure 43. SD Chroma 1.0 MHz Low-Pass Filter Response 0 0 –10 –10 –20 –20 MAGNITUDE (dB) Figure 40. SD Chroma 3.0 MHz Low-Pass Filter Response –30 –40 –40 –60 –60 2 4 8 6 FREQUENCY (MHz) 10 12 06399-042 –50 –70 Figure 41. SD Chroma 2.
ADV7342/ADV7343 0 –10 –10 –20 –20 –30 –40 –30 –40 –50 –50 –60 –60 –70 0 2 4 8 6 FREQUENCY (MHz) 10 12 Figure 45. SD Chroma CIF Low-Pass Filter Response –70 0 2 4 8 6 FREQUENCY (MHz) 10 Figure 46. SD Chroma QCIF Low-Pass Filter Response Rev.
ADV7342/ADV7343 Data Sheet MPU PORT DESCRIPTION Devices such as a microprocessor can communicate with the ADV7342/ADV7343 through a 2-wire serial (I2C-compatible) bus. After power-up or reset, the MPU port is configured for I2C operation. I2C OPERATION The ADV7342/ADV7343 support a 2-wire serial (I2C-compatible) microprocessor bus driving multiple peripherals. This port operates in an open-drain configuration.
Data Sheet ADV7342/ADV7343 SCL S 9 1–7 8 START ADDR R/W ACK 9 1–7 8 SUBADDRESS ACK 1–7 DATA 8 9 ACK P STOP 06399-049 SDA Figure 49. I2C Data Transfer S SLAVE ADDR A(S) SUBADDR A(S) DATA S SLAVE ADDR S = START BIT P = STOP BIT A(S) A(S) P LSB = 1 LSB = 0 READ SEQUENCE DATA A(S) SUBADDR A(S) S SLAVE ADDR A(S) = ACKNOWLEDGE BY SLAVE A(M) = ACKNOWLEDGE BY MASTER A(S) DATA A(M) A (S) = NO-ACKNOWLEDGE BY SLAVE A (M) = NO-ACKNOWLEDGE BY MASTER Figure 50.
ADV7342/ADV7343 Data Sheet REGISTER MAP ACCESS A microprocessor can read from or write to all registers of the ADV7342/ADV7343 via the MPU port, except for registers that are specified as read-only or write-only registers. REGISTER PROGRAMMING Table 17 to Table 35 describe the functionality of each register. All registers can be read from as well as written to, unless otherwise stated. The subaddress register determines which register the next read or write operation accesses.
Data Sheet SR7 to SR0 0x02 Register Mode Register 0 ADV7342/ADV7343 Bit Description Reserved HD interlace external VSYNC and HSYNC 7 6 Bit Number1 5 4 3 2 0 1 Manual CSC matrix adjust 0 1 Sync on RGB 0 1 RGB/YPrPb output select 0 1 SD sync output enable 0x03 0x04 0x05 0x06 0x07 0x08 0x09 1 2 3 0 1 0 1 Register Setting 0 must be written to this bit Default If using HD HSYNC/VSYNCinterlace mode, setting this bit to 1 is recommended (see the HD Interlace External P_HSYNC and P_VSYNC Considerat
ADV7342/ADV7343 Data Sheet Table 19.
Data Sheet ADV7342/ADV7343 Table 20. Register 0x12 to Register 0x17 SR7 to SR0 0x12 0x13 0x14 0x16 Register Pixel port readback (S bus) Pixel port readback (Y bus) Pixel port readback (C bus) Control port readback Bit Description S[7:0] readback Y[7:0] readback C[7:0] readback P_BLANK 7 x x x 6 x x x Bit Number 1 5 4 3 2 x x x x x x x x x x x x Reset Value 0xXX 0xXX 0xXX 0xXX x S_VSYNC x S_HSYNC SFL Reserved Reserved Software reset x 0 0 0 0 1 Reserved 1 Register Setting Read only. Read only.
ADV7342/ADV7343 Data Sheet Table 22.
Data Sheet ADV7342/ADV7343 Table 23.
ADV7342/ADV7343 Data Sheet Table 24.
Data Sheet ADV7342/ADV7343 Table 25.
ADV7342/ADV7343 Data Sheet Table 26.
Data Sheet ADV7342/ADV7343 Table 27.
ADV7342/ADV7343 Data Sheet Table 28.
Data Sheet ADV7342/ADV7343 Table 29.
ADV7342/ADV7343 SR7 to SR0 0x88 Register SD Mode Register 7 Data Sheet Bit Description Reserved SD noninterlaced mode 7 6 Bit Number 5 4 3 2 0 1 SD input format 0 0 1 1 SD digital noise reduction SD Mode Register 8 0 1 0 1 0 1 SD gamma correction enable 0x89 0 1 0 1 SD undershoot limiter 0 0 1 1 Reserved SD black burst output on DAC luma 1 0 1 0 1 0 0 1 SD chroma delay Reserved 0 0 0 1 SD double buffering SD gamma correction curve select 1 0 0 1 1 0 0 1 0 1 0 Register Settin
Data Sheet SR7 to SR0 0x8B Register SD Timing Register 1 (applicable in master modes only, that is, Subaddress 0x8A, Bit 0 = 1) ADV7342/ADV7343 Bit Description SD HSYNC width 7 6 Bit Number 1 5 4 3 2 SD HSYNC to VSYNC delay SD HSYNC to VSYNC rising edge delay (Mode 1 only) SD VSYNC width (Mode 2 only) X2 X2 0 0 1 1 0 1 0 1 0 1 0 0 1 1 0 1 0 1 1 0 0 1 1 0 0 1 0 1 0x8C SD FSC Register 0 3 Subcarrier Frequency Bits[7:0] 0 0 1 1 x 0x8D SD FSC Register 13 Subcarrier Frequency Bits[15:8] x x
ADV7342/ADV7343 Data Sheet Table 31.
Data Sheet SR7 to SR0 0xA4 Register SD DNR 1 ADV7342/ADV7343 Bit Description DNR threshold 7 Border area Block size control 0xA5 SD DNR 2 6 Bit Number 1 5 4 3 2 0 0 0 0 0 0 0 0 … … … … 1 1 1 1 1 1 1 1 0 1 1 0 1 0 1 0 Register Setting 0 1 … 62 63 Two pixels Four pixels Eight pixels 16 pixels Filter A Filter B Filter C Filter D DNR mode DNR sharpness mode 0 pixel offset One pixel offset … 14 pixel offset 15 pixel offset 0 1 0 0 0 1 DNR mode 1 0 0 1 … 0 1 0 1 DNR input select DNR block offset
ADV7342/ADV7343 SR7 to SR0 0xBB 1 2 Register Field count Data Sheet Bit Description Field count Reserved Encoder version code 7 6 0 0 0 1 Bit Number 1 5 4 3 2 x 0 0 0 1 x 0 x Register Setting Read only Reserved Read only; first encoder version 2 Read only; second encoder version Reset Value 0x0X x = Logic 0 or Logic 1. See the HD Interlace External P_HSYNC and P_VSYNC Considerations section for information about the first encoder revision. Table 33.
Data Sheet ADV7342/ADV7343 Table 35.
ADV7342/ADV7343 Data Sheet INPUT CONFIGURATION 16-Bit 4:2:2 YCrCb Mode Subaddress 0x87, Bit 7 = 0; Subaddress 0x88, Bit 3 = 1 The ADV7342/ADV7343 support a number of different input modes. The desired input mode is selected using Subaddress 0x01, Bits[6:4]. The ADV7342/ADV7343 default to standard definition only (SD only) on power-up. Table 36 provides an overview of all possible input configurations. Each input mode is described in detail in the following sections.
Data Sheet ADV7342/ADV7343 24-Bit 4:4:4 YCrCb Mode Subaddress 0x35, Bit 1 = 0; Subaddress 0x33, Bit 6 = 0 ADV7342/ ADV7343 S_VSYNC, S_HSYNC In 24-bit 4:4:4 YCrCb input mode, the Y pixel data is input on Pin Y7 to Pin Y0, with Pin Y0 being the LSB. 27MHz CLKIN_A The Cr pixel data is input on Pin S7 to Pin S0, with Pin S0 being the LSB. The Cb pixel data is input on Pin C7 to Pin C0, with Pin C0 being the LSB. 8 YCrCb 06399-051 S[7:0] OR Y[7:0]* *SELECTED BY SUBADDRESS 0x01, BIT 7.
ADV7342/ADV7343 Data Sheet Whether the ED/HD Y data is clocked in on the rising or falling edge of CLKIN_B is determined by Subaddress 0x01, Bits[2:1] (see the input sequence shown in Figure 52 and Figure 53). 2 27MHz The interleaved pixel data is input on Pin Y7 to Pin Y0, with Pin Y0 being the LSB. C[7:0] 8 Y[7:0] P_VSYNC, P_HSYNC, P_BLANK 3 74.25MHz CLKIN_B CLKIN_A Y[7:0] 3FF 00 00 XY Cb0 Y0 Cr0 Y1 Figure 57. ED Only (at 54 MHz) Input Sequence (EAV/SAV) Figure 55.
Data Sheet ADV7342/ADV7343 OUTPUT CONFIGURATION The ADV7342/ADV7343 support a number of different output configurations. Table 37 to Table 40 list all possible output configurations. Table 37.
ADV7342/ADV7343 Data Sheet DESIGN FEATURES OUTPUT OVERSAMPLING The ADV7342/ADV7343 include two on-chip phase-locked loops (PLLs) that allow for oversampling of SD, ED, and HD video data. Table 41 shows the various oversampling rates supported in the ADV7342/ADV7343. SD Only, ED Only, and HD Only Modes PLL 1 is used in SD only, ED only, and HD only modes. PLL 2 is unused in these modes. PLL 1 is disabled by default and can be enabled using Subaddress 0x00, Bit 1 = 0.
Data Sheet ADV7342/ADV7343 HD INTERLACE EXTERNAL P_HSYNC AND P_VSYNC CONSIDERATIONS ED/HD TIMING RESET If the encoder revision code (Subaddress 0xBB, Bits[7:6]) = 01 or higher, the user should set Subaddress 0x02, Bit 1 to high to ensure exactly correct timing in HD interlace modes when using the P_HSYNCand P_VSYNC synchronization signals. If this bit is set to low, the first active pixel on each line is masked and the Pr and Pb outputs are swapped when using the YCrCb 4:2:2 input format.
ADV7342/ADV7343 Data Sheet For example, in NTSC mode SD VCR FF/RW SYNC Subaddress 0x82, Bit 5 In DVD record applications where the encoder is used with a decoder, the VCR FF/RW sync control bit can be used for nonstandard input video, that is, in fast forward or rewind mode. In fast forward mode, the sync information at the start of a new field in the incoming video usually occurs before the correct number of lines/fields is reached.
Data Sheet ADV7342/ADV7343 SD SQUARE PIXEL MODE Subaddress 0x82, Bit 4 The ADV7342/ADV7343 support an SD square pixel mode (Subaddress 0x82, Bit 4). For NTSC operation, an input clock of 24.5454 MHz is required. The active resolution is 640 × 480. For PAL operation, an input clock of 29.5 MHz is required. The active resolution is 768 × 576. For CVBS and S-Video (Y-C) outputs, the SD subcarrier frequency registers must be updated to reflect the input clock frequency used in SD square pixel mode.
ADV7342/ADV7343 Data Sheet EXTENDED (SSAF) PrPb FILTER MODE FILTERS 0 Table 43 shows an overview of the programmable filters available on the ADV7342/ADV7343. –10 Table 43. Selectable Filters –20 Subaddress 0x80 0x80 0x80 0x80 0x80 0x80 0x80 0x80 0x80 0x80 0x80 0x80 0x80 0x80 0x82 0x33 0x33 0x33 GAIN (dB) –30 –40 –50 –60 0 1 2 3 4 FREQUENCY (MHz) 5 6 06399-066 Filter SD Luma LPF NTSC SD Luma LPF PAL SD Luma Notch NTSC SD Luma Notch PAL SD Luma SSAF SD Luma CIF SD Luma QCIF SD Chroma 0.
Data Sheet ADV7342/ADV7343 Table 45. Sample Color Values for EIA 770.2/EIA 770.3 ED/HD Output Standard Selection ED/HD Sinc Compensation Filter Response Subaddress 0x33, Bit 3 The ADV7342/ADV7343 include a filter designed to counter the effect of sinc roll-off in DAC 1, DAC 2, and DAC 3 while operating in ED/HD mode. This filter is enabled by default. It can be disabled using Subaddress 0x33, Bit 3. The benefit of the filter is illustrated in Figure 63 and Figure 64. 0.5 0.4 GAIN (dB) 0.
ADV7342/ADV7343 Data Sheet The SD CSC matrix scalar uses the following equations: Table 49. ED/HD Manual CSC Matrix Default Values Y = (a1 × R) + (a2 × G) + (a3 × B) + a4 Pr = (b1 × R) + (b2 × G) + (b3 × B) + b4 Pb = (c1 × R) + (c2 × G) + (c3 × B) + c4 The coefficients and their default values and register locations are shown in Table 48. Table 48.
Data Sheet ADV7342/ADV7343 SD LUMA AND COLOR SCALE CONTROL For example, to adjust the hue by +4°, write 0x97 to the hue adjust control register. Subaddress 0x9C to Subaddress 0x9F When enabled, the SD luma and color scale control feature can be used to scale the SD Y, Cb, and Cr output levels. This feature can be enabled using Subaddress 0x87, Bit 0. This feature affects all SD output signals, that is, CVBS, Y-C, YPrPb, and RGB.
ADV7342/ADV7343 Data Sheet To add a –7 IRE brightness level to a PAL signal, write 0x72 to Subaddress 0xA1. 0 × (SD Brightness Value) = 0 × (7 × 2.015631) = 0x(14.109417) ≈ 0001110b 0001110b into twos complement = 1110010b = 0x72 Table 50. Sample Brightness Control Values1 Setup Level (PAL) 15 IRE 7.5 IRE 0 IRE −7.5 IRE Brightness Control Value 0x1E 0x0F 0x00 0x71 When enabled, the ADV7342/ADV7343 can automatically identify an NTSC or a PAL B/D/G/H/I input stream.
Data Sheet ADV7342/ADV7343 DOUBLE BUFFERING Subaddress 0x33, Bit 7 for ED/HD; Subaddress 0x88, Bit 2 for SD Double-buffered registers are updated once per field. Double buffering improves overall performance because modifications to register settings are not made during active video but take effect prior to the start of the active video on the next field.
ADV7342/ADV7343 Data Sheet SD gamma correction is enabled using Subaddress 0x88, Bit 6. SD Gamma Correction Curve A is programmed at Subaddress 0xA6 to Subaddress 0xAF, and SD Gamma Correction Curve B is programmed at Subaddress 0xB0 to Subaddress 0xB9. Gamma correction is performed on the luma data only. The user can choose one of two correction curves, Curve A or Curve B. Only one of these curves can be used at a time.
Data Sheet ADV7342/ADV7343 ED/HD SHARPNESS FILTER AND ADAPTIVE FILTER CONTROLS Subaddress 0x40; Subaddress 0x58 to Subaddress 0x5D There are three filter modes available on the ADV7342/ADV7343: a sharpness filter mode and two adaptive filter modes.
ADV7342/ADV7343 Data Sheet d a R2 1 e b R4 R1 f c 1 500mV 4.00µs M 4.00µs 1 9.99978ms CH1 ALL FIELDS CH1 500mV REF A 500mV 4.00µs 1 M 4.00µs 9.99978ms CH1 ALL FIELDS 06399-074 R2 CH1 500mV REF A Figure 70. ED/ HD Sharpness Filter Control with Different Gain Settings for ED/HD Sharpness Filter Gain Values ED/HD SHARPNESS FILTER AND ADAPTIVE FILTER APPLICATION EXAMPLES Sharpness Filter Application The ED/HD sharpness filter can be used to enhance or attenuate the Y video output signal.
Data Sheet ADV7342/ADV7343 When the adaptive filter mode is changed to Mode B (Subaddress 0x35, Bit 6), the output shown in Figure 73 can be obtained. DNR MODE DNR CONTROL BLOCK SIZE CONTROL BORDER AREA BLOCK OFFSET GAIN NOISE SIGNAL PATH CORING GAIN DATA CORING GAIN BORDER INPUT FILTER BLOCK FILTER OUTPUT < THRESHOLD? Y DATA INPUT FILTER OUTPUT > THRESHOLD – SUBTRACT SIGNAL IN THRESHOLD RANGE FROM ORIGINAL SIGNAL + DNR OUT 06399-077 MAIN SIGNAL PATH DNR SHARPNESS MODE Figure 73.
ADV7342/ADV7343 APPLY DATA CORING GAIN Data Sheet DNR Input Select Control—Subaddress 0xA5, Bits[2:0] APPLY BORDER CORING GAIN Three bits are assigned to select the filter, which is applied to the incoming Y data. The signal that lies in the pass band of the selected filter is the signal that is DNR processed. Figure 77 shows the filter responses selectable with this control.
Data Sheet ADV7342/ADV7343 LUMA CHANNEL WITH ACTIVE VIDEO EDGE DISABLED LUMA CHANNEL WITH ACTIVE VIDEO EDGE ENABLED 100 IRE 100 IRE 87.5 IRE 50 IRE 0 IRE 06399-082 12.5 IRE 0 IRE Figure 78. Example of Active Video Edge Functionality VOLTS IRE:FLT 100 0.5 50 0 F2 L135 –50 0 2 4 6 8 10 12 06399-083 0 Figure 79. Example of Video Output with Subaddress 0x82, Bit 7 = 0 VOLTS IRE:FLT 100 0.5 50 0 F2 L135 –50 –2 0 2 4 6 8 10 Figure 80.
ADV7342/ADV7343 Data Sheet EXTERNAL HORIZONTAL AND VERTICAL SYNCHRONIZATION CONTROL For timing synchronization purposes, the ADV7342/ADV7343 are able to accept either EAV/SAV time codes embedded in the input pixel data or external synchronization signals provided on the S_HSYNC, S_VSYNC, P_HSYNC, P_VSYNC, and P_BLANK pins (see Table 54). It is also possible to output synchronization signals on the S_HSYNC and S_VSYNC pins (see Table 55 to Table 57). Table 54.
Data Sheet ADV7342/ADV7343 Table 57.
ADV7342/ADV7343 Data Sheet SLEEP MODE The ADV7342/ADV7343 include a power-on reset (POR) circuit to ensure correct operation after power-up. Subaddress 0x00, Bit 0 SD TELETEXT INSERTION In sleep mode, most of the digital I/O pins of the ADV7342/ ADV7343 are disabled. For inputs, this means that the external data is ignored, and internally the logic normally driven by a given input is just tied low or high. This includes CLKINx.
Data Sheet ADV7342/ADV7343 tSYNTTXOUT CVBS/Y tPD tPD HSYNC 10.2µs TTXDATA TTXDEL TTXREQ PROGRAMMABLE PULSE EDGES tSYNTTXOUT = 10.2µs. tPD = PIPELINE DELAY THROUGH ADV7342/ADC7343. TTXDEL = TTXREQ TO TTXDATA (PROGRAMMABLE RANGE = 4 BITS [0 TO 15 PIXEL CLOCK CYCLES]). Figure 82. Teletext Functionality Diagram Rev.
ADV7342/ADV7343 Data Sheet PRINTED CIRCUIT BOARD LAYOUT AND DESIGN UNUSED PINS If the S_HSYNC, S_VSYNC, P_HSYNC, and P_VSYNC pins are not used, they should be tied to VDD_IO through a pull-up resistor (10 kΩ or 4.7 kΩ). Any other unused digital inputs should be tied to ground. Unused digital output pins should be left floating. DAC outputs can be either left floating or connected to GND. Disabling these outputs is recommended. DAC CONFIGURATIONS The ADV7342/ADV7343 contain six DACs.
Data Sheet ADV7342/ADV7343 DAC OUTPUT CIRCUIT FREQUENCY RESPONSE 0 300Ω 1 75Ω 390nH 33pF 4 33pF 75Ω 200 MAGNITUDE (dB) BNC OUTPUT 3 PHASE (Degrees) –10 120 1 GROUP DELAY (Seconds) 06399-087 500Ω 500Ω Figure 85.
ADV7342/ADV7343 Data Sheet External filter and buffer components connected to the DAC outputs should be placed as close as possible to the ADV7342/ ADV7343 to minimize the possibility of noise pickup from neighboring circuitry and to minimize the effect of trace capacitance on output bandwidth. This is particularly important when operating in low-drive mode (RSETx = 4.12 kΩ, RL = 300 Ω).
Data Sheet ADV7342/ADV7343 TYPICAL APPLICATION CIRCUIT FERRITE BEAD 33µF 10µF GND_IO GND_IO FERRITE BEAD PVDD (1.8V) 33µF 10µF PGND PGND FERRITE BEAD VAA 33µF 33µF DGND 0.01µF GND_IO GND_IO 0.1µF 0.01µF PGND 10µF PVDD POWER SUPPLY DECOUPLING PGND AGND AGND VDD POWER SUPPLY DECOUPLING FOR EACH POWER PIN 0.01µF 0.1µF DGND VAA POWER SUPPLY AGND DECOUPLING DGND DGND CLOCK INPUTS I2C PORT 170Ω 12nF 150nF 1.235V VDD_IO VAA PVDD VDD VDD ADV7342/ADV7343 AD1580 0.
ADV7342/ADV7343 Data Sheet COPY GENERATION MANAGEMENT SYSTEM SD CGMS Subaddress 0x99 to Subaddress 0x9B The ADV7342/ADV7343 support a copy generation management system (CGMS) conforming to the EIAJ CPR1204 and ARIB TR-B15 standards. CGMS data is transmitted on Line 20 of odd fields and Line 283 of even fields. Subaddress 0x99, Bits[6:5] control whether CGMS data is output on odd or even fields or both. SD CGMS data can be transmitted only when the ADV7342/ ADV7343 are configured in NTSC mode.
Data Sheet ADV7342/ADV7343 +100 IRE CRC SEQUENCE REF +70 IRE C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 0 IRE –40 IRE 06399-092 49.1µs ± 0.5µs 11.2µs 2.235µs ± 20ns Figure 90. Standard Definition CGMS Waveform CRC SEQUENCE +700mV REF BIT 1 BIT 2 BIT 20 70% ± 10% C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 0mV –300mV T = 1/(fH × 33) = 963ns fH = HORIZONTAL SCAN FREQUENCY T ± 30ns 06399-093 21.2µs ± 0.22µs 22T 5.8µs ± 0.15µs 6T Figure 91.
ADV7342/ADV7343 Data Sheet CRC SEQUENCE +700mV REF BIT 1 BIT 2 BIT 20 70% ± 10% C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 0mV T ± 30ns 22.84µs ± 210ns 22T T = 1/(fH × 2200/77) = 1.038µs fH = HORIZONTAL SCAN FREQUENCY 1H 4T 4.15µs ± 60ns 06399-096 –300mV Figure 94. High Definition (1080i) CGMS Waveform CRC SEQUENCE +700mV START 70% ± 10% BIT 1 BIT 2 H0 H1 BIT 134 H2 H3 H4 H5 P0 P1 P2 P3 P4 . . .
Data Sheet ADV7342/ADV7343 SD WIDE SCREEN SIGNALING Figure 97). The latter portion of Line 23 (after 42.5 µs from the falling edge of HSYNC) is available for the insertion of video. WSS data transmission on Line 23 can be enabled using Subaddress 0x99, Bit 7. It is possible to blank the WSS portion of Line 23 with Subaddress 0xA1, Bit 7. Subaddress 0x99, Subaddress 0x9A, Subaddress 0x9B The ADV7342/ADV7343 support wide screen signaling (WSS) conforming to the ETSI 300 294 standard.
ADV7342/ADV7343 Data Sheet SD CLOSED CAPTIONING and Line 284. All pixels inputs are ignored on Line 21 and on Line 284 if closed captioning is enabled. Subaddress 0x91 to Subaddress 0x94 The ADV7342/ADV7343 support closed captioning conforming to the standard television synchronizing waveform for color transmission. Closed captioning is transmitted during the blanked active line time of Line 21 of the odd fields and Line 284 of the even fields. The FCC Code of Federal Regulations (CFR) 47 Section 15.
Data Sheet ADV7342/ADV7343 INTERNAL TEST PATTERN GENERATION SD TEST PATTERNS ED/HD TEST PATTERNS The ADV7342/ADV7343 are able to internally generate SD color bar and black bar test patterns. For this function, a 27 MHz clock signal must be applied to the CLKIN_A pin. The ADV7342/ADV7343 are able to internally generate ED/HD black bar and hatch test patterns. For ED test patterns, a 27 MHz clock signal must be applied to the CLKIN_A pin. For HD test patterns, a 74.
ADV7342/ADV7343 Data Sheet SD TIMING Mode 0 (CCIR-656)—Slave Option (Subaddress 0x8A = X X X X X 0 0 0) The ADV7342/ADV7343 are controlled by the SAV (start of active video) and EAV (end of active video) time codes embedded in the pixel data. All timing information is transmitted using a 4-byte synchronization pattern. A synchronization pattern is sent immediately before and after each line during active picture and retrace.
Data Sheet ADV7342/ADV7343 DISPLAY DISPLAY VERTICAL BLANK 622 623 624 625 1 2 4 3 5 6 21 7 22 23 H ODD FIELD EVEN FIELD F DISPLAY DISPLAY VERTICAL BLANK 309 310 311 312 314 313 315 316 318 317 319 335 334 320 336 ODD FIELD F 06399-103 H EVEN FIELD Figure 101. SD Master Mode 0, PAL ANALOG VIDEO 06399-104 H F Figure 102.
ADV7342/ADV7343 Data Sheet DISPLAY DISPLAY 622 623 VERTICAL BLANK 624 625 1 2 4 3 5 6 7 21 22 23 HSYNC FIELD EVEN FIELD ODD FIELD DISPLAY DISPLAY 309 310 VERTICAL BLANK 311 312 313 314 315 316 317 318 319 320 334 335 336 ODD FIELD FIELD 06399-106 HSYNC EVEN FIELD Figure 104. SD Slave Mode 1, PAL Mode 1—Master Option (Subaddress 0x8A = X X X X X 0 1 1) In this mode, the ADV7342/ADV7343 can generate horizontal sync and odd/even field signals.
Data Sheet ADV7342/ADV7343 DISPLAY 522 DISPLAY VERTICAL BLANK 523 524 525 1 4 3 2 5 7 6 8 10 9 20 11 21 22 HSYNC VSYNC ODD FIELD EVEN FIELD DISPLAY DISPLAY VERTICAL BLANK 260 261 262 263 264 265 266 267 268 269 270 271 272 273 283 274 284 285 VSYNC 06399-108 HSYNC EVEN FIELD ODD FIELD Figure 106.
ADV7342/ADV7343 Data Sheet HSYNC VSYNC PAL = 864 × CLOCK/2 NTSC = 858 × CLOCK/2 PIXEL DATA Cb Y Cr Cb 06399-111 Y PAL = 132 × CLOCK/2 NTSC = 122 × CLOCK/2 Figure 109. SD Timing Mode 2, Odd-to-Even Field Transition (Master/Slave) Mode 3—Master/Slave Option (Subaddress 0x8A = X X X X X 1 1 0 or X X X X X 1 1 1) In this mode, the ADV7342/ADV7343 accept or generate horizontal sync and odd/even field signals.
Data Sheet ADV7342/ADV7343 HD TIMING DISPLAY FIELD 1 VERTICAL BLANKING INTERVAL 1124 1125 1 2 3 4 5 6 7 8 20 21 22 560 P_VSYNC P_HSYNC DISPLAY VERTICAL BLANKING INTERVAL FIELD 2 561 562 563 564 565 566 567 568 569 570 583 584 585 1123 06399-114 P_VSYNC P_HSYNC Figure 112. 1080i HSYNC and VSYNC Input Timing Rev.
ADV7342/ADV7343 Data Sheet VIDEO OUTPUT LEVELS SD YPrPb OUTPUT LEVELS—SMPTE/EBU N10 BLACK BLUE RED MAGENTA GREEN CYAN 700mV YELLOW WHITE BLACK BLUE RED MAGENTA GREEN CYAN YELLOW WHITE Pattern: 100% Color Bars 700mV 300mV 06399-118 06399-115 300mV Figure 113. Y Levels—NTSC BLACK BLUE RED MAGENTA GREEN CYAN YELLOW WHITE BLACK BLUE RED MAGENTA GREEN CYAN YELLOW WHITE Figure 116. Y Levels—PAL 700mV 06399-119 06399-116 700mV Figure 114.
Data Sheet ADV7342/ADV7343 ED/HD YPrPb OUTPUT LEVELS INPUT CODE EIA-770.2, STANDARD FOR Y INPUT CODE OUTPUT VOLTAGE EIA-770.3, STANDARD FOR Y OUTPUT VOLTAGE 940 940 700mV 700mV 64 64 300mV 300mV EIA-770.3, STANDARD FOR Pr/Pb EIA-770.2, STANDARD FOR Pr/Pb OUTPUT VOLTAGE OUTPUT VOLTAGE 960 960 600mV 512 700mV 64 06399-123 700mV 64 06399-121 512 Figure 121. EIA-770.3 Standard Output Signals (1080i/720p) Figure 119. EIA-770.
ADV7342/ADV7343 Data Sheet SD/ED/HD RGB OUTPUT LEVELS Pattern: 100%/75% Color Bars R R 700mV/525mV 700mV/525mV 300mV 300mV G G 700mV/525mV 700mV/525mV 300mV 300mV B B 06399-125 300mV 300mV 06399-127 700mV/525mV 700mV/525mV Figure 125. HD RGB Output Levels—RGB Sync Disabled Figure 123.
Data Sheet ADV7342/ADV7343 SD OUTPUT PLOTS VOLTS VOLTS IRE:FLT 0.6 100 0.4 0.5 50 0.2 0 0 0 –0.2 10 L608 30 40 50 60 MICROSECONDS PRECISION MODE OFF APL = 44.5% SYNCHRONOUS SYNC = A 525 LINE NTSC µ FRAMES SELECTED 1, 2 SLOW CLAMP TO 0.00V AT 6.72µs 0 20 30 40 50 60 MICROSECONDS NOISE REDUCTION: 0.00dB PRECISION MODE OFF APL = 39.1% SYNCHRONOUS SOUND-IN-SYNC OFF 625 LINE NTSC NO FILTERING FRAMES SELECTED 1, 2, 3, 4 SLOW CLAMP TO 0.00 AT 6.72µs 20 10 Figure 127.
ADV7342/ADV7343 Data Sheet VIDEO STANDARDS 0HDATUM SMPTE 274M ANALOG WAVEFORM DIGITAL HORIZONTAL BLANKING *1 272T 4T ANCILLARY DATA (OPTIONAL) OR BLANKING CODE EAV CODE 1920T DIGITAL ACTIVE LINE F 0 0 F C V b Y C r F 0 0 H* 0 0 F 0 0 V H* F F INPUT PIXELS 4T SAV CODE 4 CLOCK SAMPLE NUMBER 2112 C Y r 4 CLOCK 0 2199 2116 2156 44 188 192 2111 06399-135 FVH* = FVH AND PARITY BITS SAV/EAV: LINE 1–562: F = 0 SAV/EAV: LINE 563–1125: F = 1 SAV/EAV: LINE 1–20; 561–583; 1124–1125: V = 1 SAV/EA
Data Sheet ADV7342/ADV7343 622 623 ACTIVE VIDEO VERTICAL BLANK 624 625 1 2 5 4 6 7 8 9 10 12 11 13 43 44 45 06399-138 ACTIVE VIDEO Figure 136. ITU-R BT.1358 (625p) DISPLAY 747 748 749 4 3 2 1 750 7 6 5 8 25 26 27 744 745 06399-139 VERTICAL BLANKING INTERVAL Figure 137.
ADV7342/ADV7343 Data Sheet CONFIGURATION SCRIPTS The scripts listed in the following pages can be used to configure the ADV7342/ ADV7343 for basic operation. Certain features are enabled by default. If required for a specific application, additional features can be enabled. Table 64 lists the scripts available for the SD modes of operation. Similarly, Table 85 and Table 111 list the scripts available for ED and HD modes of operation, respectively.
Data Sheet ADV7342/ADV7343 Table 69. 16-Bit 525i YCrCb In, YPrPb and CVBS/Y-C Out Table 65. 8-Bit 525i YCrCb In (EAV/SAV), YPrPb and CVBS/Y-C Out Subaddress 0x17 0x00 0x01 0x80 Setting 0x02 0xFC 0x00 0x10 0x82 0xC9 Description Software reset. All DACs enabled. PLL enabled (16×). SD input mode. NTSC standard. SSAF luma filter enabled. 1.3 MHz chroma filter enabled. Pixel data valid. YPrPb and CVBS/Y-C out. SSAF PrPb filter enabled. Active video edge control enabled. Pedestal enabled.
ADV7342/ADV7343 Data Sheet Table 72. 24-Bit 525i RGB In, RGB and CVBS/Y-C Out Subaddress 0x17 0x00 0x01 0x02 Setting 0x02 0xFC 0x00 0x10 0x80 0x10 0x82 0xC9 0x87 0x88 0x8A 0x80 0x10 0x0C Description Software reset. All DACs enabled. PLL enabled (16×). SD input mode. RGB output enabled. RGB output sync enabled. NTSC standard. SSAF luma filter enabled. 1.3 MHz chroma filter enabled. Pixel data valid. RGB and CVBS/Y-C out. SSAF PrPb filter enabled. Active video edge control enabled. Pedestal enabled.
Data Sheet ADV7342/ADV7343 Table 79. 16-Bit 625i YCrCb In, YPrPb and CVBS/Y-C Out Table 82. 24-Bit 625i RGB In, RGB and CVBS/Y-C Out Subaddress 0x17 0x00 0x01 0x80 Setting 0x02 0xFC 0x00 0x11 Subaddress 0x17 0x00 0x01 0x02 Setting 0x02 0xFC 0x00 0x10 0x82 0xC1 0x80 0x11 0x82 0xC1 0x88 0x8A 0x08 0x0C 0x87 0x88 0x8A 0x80 0x10 0x0C Description Software reset. All DACs enabled. PLL enabled (16×). SD input mode. PAL standard. SSAF luma filter enabled. 1.3 MHz chroma filter enabled.
ADV7342/ADV7343 Data Sheet ENHANCED DEFINITION Table 85. ED Configuration Scripts Input Format 525p at 59.94 Hz 525p at 59.94 Hz 525p at 59.94 Hz 525p at 59.94 Hz 525p at 59.94 Hz 525p at 59.94 Hz 525p at 59.94 Hz 525p at 59.94 Hz 525p at 59.94 Hz 525p at 59.94 Hz 525p at 59.94 Hz 525p at 59.
Data Sheet ADV7342/ADV7343 Table 95. 24-Bit 525p YCrCb In (EAV/SAV), RGB Out Table 90. 16-Bit 525p YCrCb In, YPrPb Out Subaddress 0x17 0x00 0x01 0x30 Setting 0x02 0x1C 0x10 0x00 0x31 0x01 Description Software reset. All DACs enabled. PLL enabled (8×). ED-SDR input mode. 525p at 59.94 Hz. HSYNC/VSYNC synchronization. EIA-770.2 output levels. Pixel data valid. Table 91.
ADV7342/ADV7343 Data Sheet Table 99. 8-Bit 625p YCrCb In, YPrPb Out Table 104. 16-Bit 625p YCrCb In (EAV/SAV), RGB Out Subaddress 0x17 0x00 0x01 Setting 0x02 0x1C 0x20 Subaddress 0x17 0x00 0x01 0x02 Setting 0x02 0x1C 0x10 0x10 0x30 0x18 0x30 0x1C 0x31 0x01 0x31 0x01 Description Software reset. All DACs enabled. PLL enabled (8×). ED-DDR input mode. Luma data clocked on falling edge of CLKIN. 625p at 50 Hz. HSYNC/VSYNC synchronization. EIA-770.2 output levels. Pixel data valid. Table 100.
Data Sheet ADV7342/ADV7343 Table 109. 24-Bit 625p YCrCb In, RGB Out Table 110. 24-Bit 625p RGB In, RGB Out Subaddress 0x17 0x00 0x01 0x02 Setting 0x02 0x1C 0x10 0x10 Subaddress 0x17 0x00 0x01 0x02 Setting 0x02 0x1C 0x10 0x10 0x30 0x18 0x30 0x18 0x31 0x33 0x01 0x28 0x31 0x33 0x35 0x01 0x28 0x02 Description Software reset. All DACs enabled. PLL enabled (8×). ED-SDR input mode. RGB output enabled. RGB output sync enabled. 625p at 50 Hz. HSYNC/VSYNC synchronization. EIA-770.2 output levels.
ADV7342/ADV7343 Data Sheet Table 112. 8-Bit 720p YCrCb In (EAV/SAV), YPrPb Out Table 116. 16-Bit 720p YCrCb In (EAV/SAV), YPrPb Out Subaddress 0x17 0x00 0x01 Setting 0x02 0x1C 0x20 Subaddress 0x17 0x00 0x01 0x30 Setting 0x02 0x1C 0x10 0x2C 0x30 0x2C 0x31 0x01 0x31 0x01 Description Software reset. All DACs enabled. PLL enabled (4×). HD-DDR input mode. Luma data clocked on falling edge of CLKIN. 720p at 60 Hz/59.94 Hz. EAV/SAV synchronization. EIA-770.3 output levels. Pixel data valid.
Data Sheet ADV7342/ADV7343 Table 120. 24-Bit 720p YCrCb In (EAV/SAV), YPrPb Out Table 124. 24-Bit 720p RGB In, RGB Out Subaddress 0x17 0x00 0x01 0x30 Setting 0x02 0x1C 0x10 0x2C Subaddress 0x17 0x00 0x01 0x02 Setting 0x02 0x1C 0x10 0x10 0x31 0x33 0x01 0x28 0x30 0x28 0x31 0x33 0x35 0x01 0x28 0x02 Description Software reset. All DACs enabled. PLL enabled (4×). HD-SDR input mode. 720p at 60 Hz/59.94 Hz. EAV/SAV synchronization. EIA-770.3 output levels. Pixel data valid. 4× oversampling.
ADV7342/ADV7343 Data Sheet Table 128. 8-Bit 1080i YCrCb In, RGB Out Table 132. 16-Bit 1080i YCrCb In, RGB Out Subaddress 0x17 0x00 0x01 Setting 0x02 0x1C 0x20 0x02 0x10 Subaddress 0x17 0x00 0x01 0x02 Setting 0x02 0x1C 0x10 0x10 0x30 0x68 0x30 0x68 0x31 0x01 0x31 0x01 Description Software reset. All DACs enabled. PLL enabled (4×). HD-DDR input mode. Luma data clocked on falling edge of CLKIN. RGB output enabled. RGB output sync enabled. 1080i at 30 Hz/29.97 Hz. EAV/SAV synchronization.
Data Sheet ADV7342/ADV7343 Table 136. 24-Bit 1080i YCrCb In, RGB Out Table 137. 24-Bit 1080i RGB In, RGB Out Subaddress 0x17 0x00 0x01 0x02 Setting 0x02 0x1C 0x10 0x10 Subaddress 0x17 0x00 0x01 0x02 Setting 0x02 0x1C 0x10 0x10 0x30 0x68 0x30 0x68 0x31 0x33 0x01 0x28 0x31 0x33 0x35 0x01 0x28 0x02 Description Software reset. All DACs enabled. PLL enabled (4×). HD-SDR input mode. RGB output enabled. RGB output sync enabled. 1080i at 30 Hz/29.97 Hz. HSYNC/VSYNC synchronization. EIA-770.
ADV7342/ADV7343 Data Sheet OUTLINE DIMENSIONS 0.75 0.60 0.45 12.20 12.00 SQ 11.80 1.60 MAX 64 49 1 48 PIN 1 10.20 10.00 SQ 9.80 TOP VIEW (PINS DOWN) 0.15 0.05 SEATING PLANE 0.20 0.09 7° 3.5° 0° 16 33 32 17 0.08 COPLANARITY VIEW A VIEW A 0.50 BSC LEAD PITCH 0.27 0.22 0.17 ROTATED 90° CCW COMPLIANT TO JEDEC STANDARDS MS-026-BCD 051706-A 1.45 1.40 1.35 Figure 139.
Data Sheet ADV7342/ADV7343 NOTES Rev.
ADV7342/ADV7343 Data Sheet NOTES I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ©2006–2012 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06399-0-3/12(D) Rev.