Data Sheet Low Power, Chip Scale, 10-Bit SD/HD Video Encoder ADV7390/ADV7391/ADV7392/ADV7393 FEATURES 3 high quality, 10-bit video DACs 16× (216 MHz) DAC oversampling for SD 8× (216 MHz) DAC oversampling for ED 4× (297 MHz) DAC oversampling for HD 37 mA maximum DAC output current Multiformat video input support 4:2:2 YCrCb (SD, ED, and HD) 4:4:4 RGB (SD) Multiformat video output support Composite (CVBS) and S-Video (Y-C) Component YPrPb (SD, ED, and HD) Component RGB (SD, ED, and HD) Lead frame chip scale
ADV7390/ADV7391/ADV7392/ADV7393 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 ED/HD Timing Reset ................................................................ 51 Revision History ............................................................................... 3 SD Subcarrier Frequency Lock ................................................. 51 Applications ..........................................................
Data Sheet ADV7390/ADV7391/ADV7392/ADV7393 ED CGMS.....................................................................................74 SD/ED/HD RGB Output Levels ................................................ 88 HD CGMS ....................................................................................74 SD Output Plots .......................................................................... 89 CGMS CRC Functionality .........................................................
ADV7390/ADV7391/ADV7392/ADV7393 Changes to ADV7390/ADV7391 Input Configuration Section .............................................................................................. 45 Added Additional Layout Considerations for the WLCSP Package Section ............................................................................... 71 Added Figure 97.............................................................................. 73 Changes to Configuration Scripts Section ..................................
Data Sheet ADV7390/ADV7391/ADV7392/ADV7393 APPLICATIONS Table 1. Standards Directly Supported by the LFCSP Packages Mobile handsets Digital still cameras Portable media and DVD players Portable game consoles Digital camcorders Set-top box (STB) Automotive infotainment (ADV7392 and ADV7393 only) Active Resolution 720 × 240 720 × 288 720 × 480 GENERAL DESCRIPTION The ADV7390/ADV7391/ADV7392/ADV7393 are a family of high speed, digital-to-analog video encoders on single monolithic chips. Three 2.7 V/3.
ADV7390/ADV7391/ADV7392/ADV7393 Data Sheet FUNCTIONAL BLOCK DIAGRAMS VBI DATA SERVICE INSERTION ALSB ADV7390/ADV7391 MPU PORT SUBCARRIER FREQUENCY LOCK (SFL) VDD_IO 8-BIT SD OR 8-BIT ED/HD SDR/DDR SD/ED/HD INPUT 4:2:2 TO 4:4:4 DEINTERLEAVE ADD SYNC PROGRAMMABLE LUMINANCE FILTER ADD BURST PROGRAMMABLE CHROMINANCE FILTER 16× FILTER YCrCb TO RGB 16× FILTER SIN/COS DDS BLOCK ASYNC BYPASS YCrCb POWER MANAGEMENT CONTROL YCbCr TO RGB MATRIX PROGRAMMABLE ED/HD FILTERS HDTV TEST PATTERN GENERAT
Data Sheet ADV7390/ADV7391/ADV7392/ADV7393 SPECIFICATIONS POWER SUPPLY SPECIFICATIONS All specifications TMIN to TMAX (−40°C to +85°C), unless otherwise noted. Table 3. Parameter SUPPLY VOLTAGES VDD VDD_IO PVDD VAA POWER SUPPLY REJECTION RATIO Min Typ Max Unit 1.71 1.71 1.71 2.6 1.8 3.3 1.8 3.3 0.002 1.89 3.63 1.89 3.465 V V V V %/% INPUT CLOCK SPECIFICATIONS VDD = 1.71 V to 1.89 V, PVDD = 1.71 V to 1.89 V, VAA = 2.6 V to 3.465 V, VDD_IO = 1.71 V to 3.63 V.
ADV7390/ADV7391/ADV7392/ADV7393 Data Sheet DIGITAL INPUT/OUTPUT SPECIFICATIONS—3.3 V VDD = 1.71 V to 1.89 V, PVDD = 1.71 V to 1.89 V, VAA = 2.6 V to 3.465 V, VDD_IO = 2.97 V to 3.63 V. All specifications TMIN to TMAX (−40°C to +85°C), unless otherwise noted. Table 6. Parameter Input High Voltage, VIH Input Low Voltage, VIL Input Leakage Current, IIN Input Capacitance, CIN Output High Voltage, VOH Output Low Voltage, VOL Three-State Leakage Current Three-State Output Capacitance Conditions Min 2.
Data Sheet ADV7390/ADV7391/ADV7392/ADV7393 DIGITAL TIMING SPECIFICATIONS—3.3 V VDD = 1.71 V to 1.89 V, PVDD = 1.71 V to 1.89 V, VAA = 2.6 V to 3.465 V, VDD_IO = 2.97 V to 3.63 V. All specifications TMIN to TMAX (−40°C to +85°C), unless otherwise noted. Table 9.
ADV7390/ADV7391/ADV7392/ADV7393 Data Sheet DIGITAL TIMING SPECIFICATIONS—1.8 V VDD = 1.71 V to 1.89 V, PVDD = 1.71 V to 1.89 V, VAA = 2.6 V to 3.465 V, VDD_IO = 1.71 V to 1.89 V. All specifications TMIN to TMAX (−40°C to +85°C), unless otherwise noted. Table 10.
Data Sheet ADV7390/ADV7391/ADV7392/ADV7393 VIDEO PERFORMANCE SPECIFICATIONS VDD = 1.8 V, PVDD = 1.8 V, VAA = 3.3 V, VDD_IO = 3.3 V, TA = +25°C. Table 11. Parameter STATIC PERFORMANCE Resolution Integral Nonlinearity (INL) 1 Differential Nonlinearity (DNL)1, 2 STANDARD DEFINTION (SD) MODE Luminance Nonlinearity Differential Gain Differential Phase Signal-to-Noise Ratio (SNR) 3 Conditions Min Typ Max Unit RSET = 510 Ω, RL = 37.5 Ω RSET = 510 Ω, RL = 37.5 Ω 10 0.5 0.
ADV7390/ADV7391/ADV7392/ADV7393 Data Sheet TIMING DIAGRAMS • t13 = control output access time • t14 = control output hold time In addition, see Table 35 for the ADV7390/ADV7391 pixel port input configuration and Table 36 for the ADV7392/ADV7393 pixel port input configuration.
Data Sheet ADV7390/ADV7391/ADV7392/ADV7393 CLKIN t9 CONTROL INPUTS t12 t10 HSYNC VSYNC PIXEL PORT G0 G1 G2 PIXEL PORT B0 B1 B2 R1 R2 t11 R0 PIXEL PORT CONTROL OUTPUTS 06234-004 t14 t13 Figure 6. SD Input, 16-Bit 4:4:4 RGB, Input Mode 000 CLKIN t9 CONTROL INPUTS t12 t10 HSYNC VSYNC PIXEL PORT Y0 Y1 Y2 Y3 Y4 Y5 PIXEL PORT Cb0 Cr0 Cb2 Cr2 Cb4 Cr4 t11 t13 06234-005 CONTROL OUTPUTS t14 Figure 7.
ADV7390/ADV7391/ADV7392/ADV7393 Data Sheet CLKIN* t9 PIXEL PORT 3FF t11 t10 00 00 XY t12 Cb0 Y0 Cr0 Y1 t12 t11 t13 t14 *LUMA/CHROMA CLOCK RELATIONSHIP CAN BE INVERTED USING SUBADDRESS 0x01, BITS 1 AND 2. 06234-007 CONTROL OUTPUTS Figure 9. ED/HD-DDR Input, 8-/10-Bit 4:2:2 YCrCb (EAV/SAV), Input Mode 010 CLKIN t10 t9 CONTROL INPUTS HSYNC VSYNC Cb0 PIXEL PORT Y0 Cr0 Y1 Cr2 Y2 t13 t12 t11 Cb2 06234-008 t14 CONTROL OUTPUTS Figure 10.
Data Sheet ADV7390/ADV7391/ADV7392/ADV7393 Y OUTPUT b HSYNC VSYNC PIXEL PORT Y0 Y1 Y2 Y3 PIXEL PORT* Cb0 Cr0 Cb2 Cr2 a a = AS PER RELEVANT STANDARD. 06234-010 b = PIPELINE DELAY. PLEASE REFER TO RELEVANT PIPELINE DELAY. THIS CAN BE FOUND IN THE DIGITAL TIMING SPECIFICATION SECTION OF THE DATA SHEET. A FALLING EDGE OF HSYNC INTO THE ENCODER GENERATES A SYNC FALLING EDGE ON THE OUTPUT AFTER A TIME EQUAL TO THE PIPELINE DELAY. Figure 12.
ADV7390/ADV7391/ADV7392/ADV7393 Data Sheet Y OUTPUT b HSYNC VSYNC PIXEL PORT Y0 Y1 Y2 Y3 PIXEL PORT Cb0 Cr0 Cb2 Cr2 a a = AS PER RELEVANT STANDARD. 06234-012 b = PIPELINE DELAY. PLEASE REFER TO RELEVANT PIPELINE DELAY. THIS CAN BE FOUND IN THE DIGITAL TIMING SPECIFICATION SECTION OF THE DATA SHEET. A FALLING EDGE OF HSYNC INTO THE ENCODER GENERATES A FALLING EDGE OF TRI-LEVEL SYNC ON THE OUTPUT AFTER A TIME EQUAL TO THE PIPELINE DELAY. Figure 14.
Data Sheet ADV7390/ADV7391/ADV7392/ADV7393 HSYNC VSYNC Cr PAL = 264 CLOCK CYCLES NTSC = 244 CLOCK CYCLES Figure 16. SD Input Timing Diagram (Timing Mode 1) t3 t5 t3 SDA t1 SCL t2 t7 t4 t8 2C Mode) Figure 17. MPU Port Timing Diagram (I Rev. J | Page 17 of 107 Downloaded from Arrow.com.
ADV7390/ADV7391/ADV7392/ADV7393 Data Sheet ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 13. Parameter VAA to AGND VDD to DGND PVDD to PGND VDD_IO to GND_IO AGND to DGND AGND to PGND AGND to GND_IO DGND to PGND DGND to GND_IO PGND to GND_IO Digital Input Voltage to GND_IO Analog Outputs to AGND Max CLKIN Input Frequency Storage Temperature Range (tS) Junction Temperature (tJ) Lead Temperature (Soldering, 10 sec) 1 1 Rating −0.3 V to +3.9 V −0.3 V to +2.3 V −0.3 V to +2.3 V −0.3 V to +3.9 V −0.
Data Sheet ADV7390/ADV7391/ADV7392/ADV7393 GND_IO P1 P0 DGND VDD HSYNC VSYNC SFL PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 32 31 30 29 28 27 26 25 BALL A1 CORNER 1 2 3 4 5 6 7 8 PIN 1 INDICATOR ADV7390/ ADV7391 TOP VIEW (Not to Scale) 24 23 22 21 20 19 18 17 RSET COMP DAC 1 DAC 2 DAC 3 VAA AGND PVDD 2 3 4 5 A RSET HSYNC VDD P0 VDD_IO B DAC1 VSYNC SFL P1 P2 C VAA COMP DGND P3 P4 D AGND GND_IO RESET VDD DGND E PVDD EXT_LF ALSB P5 P6 F PGND SDA SCL CLKIN P7 T
ADV7390/ADV7391/ADV7392/ADV7393 Data Sheet ADV7390/ ADV7391 24 Pin No.
Data Sheet ADV7390/ADV7391/ADV7392/ADV7393 TYPICAL PERFORMANCE CHARACTERISTICS ED Pr/Pb RESPONSE. LINEAR INTERP FROM 4:2:2 TO 4:4:4 Y RESPONSE IN ED 8× OVERSAMPLING MODE 1.0 0 0.5 –10 0 –0.5 GAIN (dB) –40 –1.0 –50 –1.5 –60 –2.0 –70 –2.5 –80 0 20 40 60 80 100 120 140 FREQUENCY (MHz) 160 180 200 –3.0 Figure 21. ED 8× Oversampling, PrPb Filter (Linear) Response 0 2 4 6 8 FREQUENCY (MHz) 10 06234-022 –30 06234-019 GAIN (dB) –20 12 Figure 24.
ADV7390/ADV7391/ADV7392/ADV7393 Data Sheet Y RESPONSE IN HD 4× OVERSAMPLING MODE 10 0 0 –10 –10 MAGNITUDE (dB) –20 GAIN (dB) –30 –40 –50 –60 –20 –30 –40 –50 –70 –80 –60 –70 0 18.5 37.0 55.5 74.0 92.5 FREQUENCY (MHz) 111.0 129.5 148.0 0 06234-025 –100 2 4 6 8 FREQUENCY (MHz) 10 12 06234-028 –90 Figure 30. SD PAL, Luma Low-Pass Filter Response Figure 27. HD 4× Oversampling, Y Filter Response Y PASS BAND IN HD 4x OVERSAMPLING MODE 3.0 0 1.5 –10 0 MAGNITUDE (dB) GAIN (dB) –1.
Data Sheet ADV7390/ADV7391/ADV7392/ADV7393 Y RESPONSE IN SD OVERSAMPLING MODE 5 0 4 –10 MAGNITUDE (dB) GAIN (dB) –20 –30 –40 –50 –60 3 2 1 0 –1 20 0 40 60 80 100 120 140 FREQUENCY (MHz) 160 180 0 06234-031 –80 200 3 4 FREQUENCY (MHz) 2 1 5 7 6 06234-034 –70 Figure 36. SD Luma SSAF Filter, Programmable Gain Figure 33.
Data Sheet 0 –10 –10 –20 –20 –30 –40 –50 –60 –60 2 4 8 6 FREQUENCY (MHz) 10 12 –70 0 Figure 39. SD Luma QCIF Low-Pass Filter Response –10 –10 –20 –20 MAGNITUDE (dB) 0 –30 –40 –60 –60 10 12 12 –70 06234-038 –70 8 6 FREQUENCY (MHz) 10 –40 –50 4 8 6 FREQUENCY (MHz) –30 –50 2 4 Figure 42. SD Chroma 1.3 MHz Low-Pass Filter Response 0 0 2 0 2 4 8 6 FREQUENCY (MHz) 10 Figure 43. SD Chroma 1.
ADV7390/ADV7391/ADV7392/ADV7393 0 –10 –10 –20 –20 –30 –40 –30 –40 –50 –50 –60 –60 –70 0 2 4 8 6 FREQUENCY (MHz) 10 12 Figure 45. SD Chroma CIF Low-Pass Filter Response 0 2 4 8 6 FREQUENCY (MHz) 10 Figure 46. SD Chroma QCIF Low-Pass Filter Response Rev. J | Page 25 of 107 Downloaded from Arrow.com.
ADV7390/ADV7391/ADV7392/ADV7393 Data Sheet MPU PORT DESCRIPTION Devices such as a microprocessor can communicate with the ADV7390/ADV7391/ADV7392/ADV7393 through a 2-wire serial (I2C-compatible) bus. After power-up or reset, the MPU port is configured for I2C operation. I2C OPERATION The ADV7390/ADV7391/ADV7392/ADV7393 support a 2-wire serial (I2C-compatible) microprocessor bus driving multiple peripherals. This port operates in an open-drain configuration.
Data Sheet ADV7390/ADV7391/ADV7392/ADV7393 SCL S 9 1–7 8 START ADDR R/W ACK 9 1–7 8 SUBADDRESS ACK 1–7 DATA 8 9 ACK P STOP 06234-047 SDA Figure 49. I2C Data Transfer S SLAVE ADDR A(S) SUBADDR A(S) DATA S SLAVE ADDR S = START BIT P = STOP BIT A(S) SUBADDR A(S) S SLAVE ADDR A(S) = ACKNOWLEDGE BY SLAVE A(M) = ACKNOWLEDGE BY MASTER A(S) DATA A(M) A (S) = NO-ACKNOWLEDGE BY SLAVE A (M) = NO-ACKNOWLEDGE BY MASTER Figure 50. I2C Read and Write Sequence Rev.
ADV7390/ADV7391/ADV7392/ADV7393 Data Sheet REGISTER MAP ACCESS A microprocessor can read from or write to all registers of the ADV7390/ADV7391/ADV7392/ADV7393 via the MPU port, except for registers that are specified as read-only or write-only registers. REGISTER PROGRAMMING The subaddress register determines the register accessed by the next read or write operation. All communication through the MPU port starts with an access to the subaddress register.
Data Sheet SR7 to SR0 0x02 Register Mode Register 0 ADV7390/ADV7391/ADV7392/ADV7393 Bit Description Reserved HD interlace external VSYNC and HSYNC 7 6 Bit Number 1 5 4 3 2 0 1 Manual CSC matrix adjust 0 1 Sync on RGB 0 1 RGB/YPrPb output select 0 1 SD sync output enable 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0 1 0 1 x x LSBs for GY. 0x03 x x 0xF0 0x4E x x x x x x x x x x x x LSBs for RV. LSBs for BU. LSBs for GV. LSBs for GU. Bits[9:2] for GY.
ADV7390/ADV7391/ADV7392/ADV7393 Data Sheet Table 19.
Data Sheet ADV7390/ADV7391/ADV7392/ADV7393 Table 20.
ADV7390/ADV7391/ADV7392/ADV7393 Data Sheet Table 21.
Data Sheet ADV7390/ADV7391/ADV7392/ADV7393 Table 22. Register 0x34 to Register 0x38 SR7 to SR0 0x34 Register ED/HD Mode Register 5 Bit Description ED/HD timing reset 7 6 Bit Number 1 5 4 3 2 0 1 ED/HD VSYNC control2 Reserved ED Macrovision® enable 3 0 0 1 0 = Field input. 1 = VSYNC input. Update field/line counter. Field/line counter free running.
ADV7390/ADV7391/ADV7392/ADV7393 Data Sheet Table 23.
Data Sheet ADV7390/ADV7391/ADV7392/ADV7393 Table 24.
ADV7390/ADV7391/ADV7392/ADV7393 Data Sheet Table 25.
Data Sheet ADV7390/ADV7391/ADV7392/ADV7393 Table 26.
ADV7390/ADV7391/ADV7392/ADV7393 Data Sheet Table 27.
Data Sheet ADV7390/ADV7391/ADV7392/ADV7393 Table 28.
ADV7390/ADV7391/ADV7392/ADV7393 Data Sheet Table 29.
Data Sheet SR7 to SR0 0x8B Register SD Timing Register 1 Note: Applicable in master modes only, that is, Subaddress 0x8A, Bit 0 = 1.
ADV7390/ADV7391/ADV7392/ADV7393 SR7 to SR0 Register 0x9B SD CGMS/WSS 2 0x9C SD scale LSB 0x9D 0x9E 0x9F 0xA0 0xA1 SD Y scale SD Cb scale SD Cr scale SD hue adjust SD brightness/WSS 0xA2 SD luma SSAF 0xA3 SD DNR 0 Bit Description SD CGMS data SD CGMS/WSS data LSBs for SD Y scale value LSBs for SD Cb scale value LSBs for SD Cr scale value LSBs for SD FSC phase SD Y scale value SD Cb scale value SD Cr scale value SD hue adjust value SD brightness value SD blank WSS data Data Sheet 7 x x x x x x x
Data Sheet SR7 to SR0 0xA4 Register SD DNR 1 ADV7390/ADV7391/ADV7392/ADV7393 Bit Description DNR threshold 7 Border area Block size 0xA5 SD DNR 2 6 Bit Number 1 5 4 3 2 0 0 0 0 0 0 0 0 … … … … 1 1 1 1 1 1 1 1 0 1 1 0 1 0 1 0 0 1 0 0 0 1 DNR mode 1 0 0 1 … 0 1 0 1 DNR input select DNR block offset 1 0 0 … 1 1 0 1 0 0 … 1 1 0 0 … 1 1 0 0 … 1 1 0 1 … 0 1 Register Setting 0 1 … 62 63 Two pixels Four pixels Eight pixels 16 pixels Filter A Filter B Filter C Filter D DNR mode DNR sharpness mo
ADV7390/ADV7391/ADV7392/ADV7393 SR7 to SR0 0xBB 1 2 Register Field count Data Sheet Bit Description Field count Reserved Encoder version code 7 6 0 0 0 1 Bit Number 1 5 4 3 2 x 0 0 0 1 x 0 x Register Setting Read only Reserved Read only; first encoder version 2 Read only; second encoder version Reset Value 0x0X x = Logic 0 or Logic 1. See the HD Interlace External HSYNC and VSYNC Considerations section for information about the first encoder version. Table 33.
Data Sheet ADV7390/ADV7391/ADV7392/ADV7393 Table 34.
ADV7390/ADV7391/ADV7392/ADV7393 Data Sheet ADV7390/ADV7391 INPUT CONFIGURATION The ADV7390/ADV7391 support a number of different input modes. The desired input mode is selected using Subaddress 0x01, Bits[6:4]. The ADV7390/ADV7391 default to standard definition (SD) mode on power-up. Table 35 provides an overview of all possible input configurations. Each input mode is described in detail in this section. Note that the WLCSP option is only configured to support SD as shown in Figure 51.
Data Sheet ADV7390/ADV7391/ADV7392/ADV7393 ADV7392/ADV7393 INPUT CONFIGURATION 16-Bit 4:2:2 YCrCb Mode Subaddress 0x87, Bit 7 = 0; Subaddress 0x88, Bits[4:3] = 01 The ADV7392/ADV7393 support a number of different input modes. The desired input mode is selected using Subaddress 0x01, Bits[6:4]. The ADV7392/ADV7393 default to standard definition (SD) mode on power-up. Table 36 provides an overview of all possible input configurations. Each input mode is described in detail in this section.
ADV7390/ADV7391/ADV7392/ADV7393 Data Sheet MPEG2 DECODER Subaddress 0x01, Bits[6:4] = 001 or 010 ED or HD YCrCb data can be input in a 4:2:2 format over an 8-/10-bit DDR bus or a 16-bit SDR bus. ADV7392/ ADV7393 CLKIN YCrCb The clock signal must be provided on the CLKIN pin. If required, external synchronization signals can be provided on the HSYNC and VSYNC pins. Embedded EAV/SAV timing codes are also supported.
Data Sheet ADV7390/ADV7391/ADV7392/ADV7393 OUTPUT CONFIGURATION The ADV7390/ADV7391/ADV7392/ADV7393 support a number of different output configurations. Table 37 to Table 39 list all possible output configurations. Table 37.
ADV7390/ADV7391/ADV7392/ADV7393 Data Sheet DESIGN FEATURES OUTPUT OVERSAMPLING The ADV7390/ADV7391/ADV7392/ADV7393 include an onchip phase-locked loop (PLL) that allows for oversampling of SD, ED, and HD video data. By default, the PLL is disabled. The PLL can be enabled using Subaddress 0x00, Bit 1 = 0. Table 40 shows the various oversampling rates supported in the ADV7390/ADV7391/ADV7392/ADV7393.
Data Sheet ADV7390/ADV7391/ADV7392/ADV7393 HD INTERLACE EXTERNAL HSYNC AND VSYNC CONSIDERATIONS ED/HD TIMING RESET If the encoder revision code (Subaddress 0xBB, Bits[7:6]) = 01 or higher, the user should set Subaddress 0x02, Bit 1 to high. To ensure correct timing in HD interlace modes when using HSYNC and VSYNC synchronization signals.
ADV7390/ADV7391/ADV7392/ADV7393 SD VCR FF/RW SYNC Data Sheet For example, in NTSC mode: Subaddress 0x82, Bit 5 In DVD record applications where the encoder is used with a decoder, the VCR FF/RW sync control bit can be used for nonstandard input video, that is, in fast forward or rewind modes. In fast forward mode, the sync information at the start of a new field in the incoming video usually occurs before the correct number of lines/fields is reached.
Data Sheet ADV7390/ADV7391/ADV7392/ADV7393 SD SQUARE PIXEL MODE Subaddress 0x82, Bit 4 The ADV7390/ADV7391/ADV7392/ADV7393 support an SD square pixel mode (Subaddress 0x82, Bit 4). For NTSC operation, an input clock of 24.5454 MHz is required. The active resolution is 640 × 480. For PAL operation, an input clock of 29.5 MHz is required. The active resolution is 768 × 576.
ADV7390/ADV7391/ADV7392/ADV7393 Data Sheet FILTERS EXTENDED (SSAF) PrPb FILTER MODE 0 Table 42 shows an overview of the programmable filters available on the ADV7390/ADV7391/ADV7392/ADV7393. –10 Table 42. Selectable Filters Subaddress 0x80 0x80 0x80 0x80 0x80 0x80 0x80 0x80 0x80 0x80 0x80 0x80 0x80 0x80 0x82 0x33 0x33 GAIN (dB) –30 –40 –50 –60 0 1 2 3 4 FREQUENCY (MHz) 5 6 Figure 66.
Data Sheet ADV7390/ADV7391/ADV7392/ADV7393 ED/HD Sinc Compensation Filter Response Subaddress 0x33, Bit 3 The ADV7390/ADV7391/ADV7392/ADV7393 include a filter designed to counter the effect of sinc roll-off in DAC 1, DAC 2, and DAC 3 while operating in ED/HD mode. This filter is enabled by default. It can be disabled using Subaddress 0x33, Bit 3. The benefit of the filter is illustrated in Figure 67 and Figure 68. 0.5 0.4 0.3 GAIN (dB) 0.2 0.1 0 Table 44. Sample Color Values for EIA770.2/EIA770.
ADV7390/ADV7391/ADV7392/ADV7393 Data Sheet Y = (a1 × R) + (a2 × G) + (a3 × B) + a4 On power-up, the CSC matrix is programmed with the default values shown in Table 48. Pr = (b1 × R) + (b2 × G) + (b3 × B) + b4 Table 48. ED/HD Manual CSC Matrix Default Values Pb = (c1 × R) + (c2 × G) + (c3 × B) + c4 Subaddress 0x03 0x04 0x05 0x06 0x07 0x08 0x09 The SD CSC matrix scalar uses the following equations: The coefficients and their default values are located in the registers shown in Table 47. Table 47.
Data Sheet ADV7390/ADV7391/ADV7392/ADV7393 For example, to adjust the hue by +4°, write 0x97 to the hue adjust control register. SD LUMA AND COLOR SCALE CONTROL Subaddress 0x9C to Subaddress 0x9F When enabled, the SD luma and color scale control feature can be used to scale the SD Y, Cb, and Cr output levels. This feature can be enabled using Subaddress 0x87, Bit 0. This feature affects all SD output signals, that is, CVBS, Y-C, YPrPb, and RGB.
ADV7390/ADV7391/ADV7392/ADV7393 To add a –7 IRE brightness level to a PAL signal, write 0x72 to Subaddress 0xA1. 0 × (SD Brightness Value) = PROGRAMMABLE DAC GAIN CONTROL Subaddress 0x0B 0 × (IRE Value × 2.075631) = It is possible to adjust the DAC output signal gain up or down from its absolute level. This is illustrated in Figure 70. 0 × (7 × 2.015631) = 0x(14.109417) ≈ 0001110b DAC 1 to DAC 3 are controlled by Register 0x0B.
Data Sheet ADV7390/ADV7391/ADV7392/ADV7393 The reset value of the control registers is 0x00; that is, nominal DAC current is output. Table 50 is an example of how the output current of the DACs varies for a nominal 4.33 mA output current. Table 50. DAC Gain Control Subaddress 0x0B 0100 0000 (0x40) 0011 1111 (0x3F) 0011 1110 (0x3E) ... ... 0000 0010 (0x02) 0000 0001 (0x01) 0000 0000 (0x00) DAC Current (mA) 4.658 4.653 4.648 ... ... 4.43 4.38 4.33 % Gain 7.5000% 7.3820% 7.3640% ... ... 0.0360% 0.0180% 0.
ADV7390/ADV7391/ADV7392/ADV7393 enabled (Subaddress 0x31, Bit 7 = 1) and the ED/HD adaptive filter must be disabled (Subaddress 0x35, Bit 7 = 0). The gamma curves in Figure 71 and Figure 72 are examples only; any user-defined curve in the range from 16 to 240 is acceptable. 250 SIGNAL OUTPUT ED/HD Adaptive Filter Mode 200 In ED/HD adaptive filter mode, the following registers are used: 0.
ADV7390/ADV7391/ADV7392/ADV7393 1.4 1.3 1.3 1.2 1.2 MAGNITUDE MAGNITUDE INPUT SIGNAL STEP 1.4 1.1 1.0 0.9 1.1 1.0 0.9 0.8 0.8 0.7 0.7 0.6 0.6 0.5 MAGNITUDE RESPONSE (Linear Scale) SHARPNESS AND ADAPTIVE FILTER CONTROL BLOCK 1.5 1.5 0.5 FREQUENCY (MHz) FILTER A RESPONSE (Gain Ka) 1.6 1.5 1.4 1.3 1.2 1.1 1.
ADV7390/ADV7391/ADV7392/ADV7393 Data Sheet In DNR mode, if the absolute value of the filter output is smaller than the threshold, it is assumed to be noise. A programmable amount (coring gain border, coring gain data) of this noise signal is subtracted from the original signal. In DNR sharpness mode, if the absolute value of the filter output is less than the programmed threshold, it is assumed to be noise as before.
Data Sheet ADV7390/ADV7391/ADV7392/ADV7393 Coring Gain Border—Subaddress 0xA3, Bits[3:0] Block Size—Subaddress 0xA4, Bit 7 These four bits are assigned to the gain factor applied to border areas. In DNR mode, the range of gain values is 0 to 1 in increments of 1/8. This factor is applied to the DNR filter output that lies below the set threshold range. The result is then subtracted from the original signal. This bit is used to select the size of the data blocks to be processed.
ADV7390/ADV7391/ADV7392/ADV7393 Data Sheet SD ACTIVE VIDEO EDGE CONTROL three pixels of the active video on the luma channel are scaled so that maximum transitions on these pixels are not possible. Subaddress 0x82, Bit 7 At the start of active video, the first three pixels are multiplied by 1/8, 1/2, and 7/8, respectively. Approaching the end of active video, the last three pixels are multiplied by 7/8, 1/2, and 1/8, respectively. All other active video pixels pass through unprocessed.
Data Sheet ADV7390/ADV7391/ADV7392/ADV7393 EXTERNAL HORIZONTAL AND VERTICAL SYNCHRONIZATION CONTROL For timing synchronization purposes, the ADV7390/ADV7391/ADV7392/ADV7393 are able to accept either EAV/SAV time codes embedded in the input pixel data or external synchronization signals provided on the HSYNC and VSYNC pins (see Table 53). It is also possible to output synchronization signals on the HSYNC and VSYNC pins (see Table 54 to Table 56). Table 53.
ADV7390/ADV7391/ADV7392/ADV7393 ED/HD Input Sync Format (Subaddress 0x30, Bit 2) X ED/HD VSYNC Control (Subaddress 0x34, Bit 2) 1 ED/HD Sync Output Enable (Subaddress 0x02, Bit 7) 1 SD Sync Output Enable (Subaddress 0x02, Bit 6) X X 1 1 X 1 2 Data Sheet Video Standard All ED/HD standards except 525p 525p Signal on VSYNC Pin Pipelined ED/HD VSYNC based on the vertical counter Pipelined ED/HD VSYNC based on the vertical counter Duration Aligned with serration lines. Vertical blanking interval.
Data Sheet ADV7390/ADV7391/ADV7392/ADV7393 PIXEL AND CONTROL PORT READBACK SD TELETEXT INSERTION Subaddress 0x13, Subaddress 0x14, Subaddress 0x16 Subaddress 0xC9 to Subaddress 0xCE The ADV7390/ADV7391/ADV7392/ADV7393 support the readback of most digital inputs via the I2C MPU port. This feature is useful for board-level connectivity testing with upstream devices. The ADV7390/ADV7391/ADV7392/ADV7393 support the insertion of teletext data, using a two pin interface, when operating in PAL mode.
ADV7390/ADV7391/ADV7392/ADV7393 Data Sheet tSYNTTXOUT CVBS/Y tPD tPD HSYNC 10.2µs TTXDATA TTXDEL TTXREQ PROGRAMMABLE PULSE EDGES tSYNTTXOUT = 10.2µs. tPD = PIPELINE DELAY THROUGH ADV7390/ADV7391/ADV7392/ADV7393. TTXDEL = TTXREQ TO TTXDATA (PROGRAMMABLE RANGE = 4 BITS [0 TO 15 PIXEL CLOCK CYCLES]). Figure 86. Teletext Functionality Diagram Rev. J | Page 68 of 107 Downloaded from Arrow.com.
Data Sheet ADV7390/ADV7391/ADV7392/ADV7393 PRINTED CIRCUIT BOARD LAYOUT AND DESIGN UNUSED PINS If the HSYNC and VSYNC pins are not used, they should be tied to VDD_IO through a pull-up resistor (10 kΩ or 4.7 kΩ). Any other unused digital inputs should be tied to ground. Unused digital output pins should be left floating. DAC outputs can either be left floating or connected to GND. Disabling these outputs is recommended. DAC CONFIGURATIONS Table 57.
ADV7390/ADV7391/ADV7392/ADV7393 CIRCUIT FREQUENCY RESPONSE 0 PRINTED CIRCUIT BOARD (PCB) LAYOUT 0 24n The ADV7390/ADV7391/ADV7392/ADV7393 are highly integrated circuits containing both precision analog and high speed digital circuitry. It is designed to minimize interference effects on the integrity of the analog circuitry by the high speed digital circuitry. It is imperative that these same design and layout techniques be applied to the system-level design so that optimal performance is achieved.
Data Sheet ADV7390/ADV7391/ADV7392/ADV7393 Power Supply Decoupling It is recommended that each power supply pin be decoupled with 10 nF and 0.1 μF ceramic capacitors. The VAA, PVDD, VDD_IO, and both VDD pins should be individually decoupled to ground. The decoupling capacitors should be placed as close as possible to the ADV7390/ADV7391/ADV7392/ADV7393 with the capacitor leads kept as short as possible to minimize lead inductance.
ADV7390/ADV7391/ADV7392/ADV7393 Data Sheet TYPICAL APPLICATIONS CIRCUITS FERRITE BEAD 3.3V 33µF VDD_IO 10µF 0.1µF GND_IO GND_IO FERRITE BEAD PVDD 1.8V 33µF GND_IO 10µF 0.1µF PGND PGND FERRITE BEAD V PGND VDD_IO POWER SUPPLY DECOUPLING 0.01µF GND_IO PVDD POWER SUPPLY DECOUPLING 0.01µF PGND NOTES 1. FOR OPTIMUM PERFORMANCE, EXTERNAL COMPONENTS CONNECTED TO THE COMP, RSET AND DAC OUTPUT PINS SHOULD BE LOCATED CLOSE TO, AND ON THE SAME SIDE OF THE PCB AS, THE ADV7390/ADV7391/ADV7392/ADV7393.
Data Sheet ADV7390/ADV7391/ADV7392/ADV7393 FERRITE BEAD 3.3V 33µF VDD_IO 10µF 0.1µF GND_IO GND_IO FERRITE BEAD PV GND_IO VDD_IO POWER 0.01µF SUPPLY DECOUPLING GND_IO DD 1.8V 33µF 10µF 0.1µF PGND PGND FERRITE BEAD VAA 3.3V 33µF PGND 33µF DGND PGND 2. THE I2C DEVICE ADDRESS IS CONFIGURABLE USING THE ALSB PIN: ALSB = 0, I2C DEVICE ADDRESS = 0xD4 ALSB = 1, I2C DEVICE ADDRESS = 0xD6 10µF 0.1µF AGND AGND FERRITE BEAD VDD 1.8V PVDD POWER SUPPLY DECOUPLING 0.01µF NOTES 1.
ADV7390/ADV7391/ADV7392/ADV7393 Data Sheet COPY GENERATION MANAGEMENT SYSTEM SD CGMS Subaddress 0x99 to Subaddress 0x9B The ADV7390/ADV7391/ADV7392/ADV7393 support a copy generation management system (CGMS) that conforms to the EIAJ CPR-1204 and ARIB TR-B15 standards. CGMS data is transmitted on Line 20 of odd fields and Line 283 of even fields. Subaddress 0x99, Bits[6:5] control whether CGMS data is output on odd or even fields or both.
Data Sheet ADV7390/ADV7391/ADV7392/ADV7393 +100 IRE CRC SEQUENCE REF +70 IRE C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 0 IRE –40 IRE 06234-093 49.1µs ± 0.5µs 11.2µs 2.235µs ± 20ns Figure 95. Standard Definition CGMS Waveform CRC SEQUENCE +700mV REF BIT 1 BIT 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ADV7390/ADV7391/ADV7392/ADV7393 Data Sheet CRC SEQUENCE +700mV REF BIT 1 BIT 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BIT 20 70% ± 10% C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 0mV T ± 30ns 22.84µs ± 210ns 22T T = 1/(fH × 2200/77) = 1.038µs fH = HORIZONTAL SCAN FREQUENCY 1H 4T 4.15µs ± 60ns 06234-097 –300mV Figure 99.
Data Sheet ADV7390/ADV7391/ADV7392/ADV7393 SD WIDE SCREEN SIGNALING sequence and a start code (see Figure 102). The latter portion of Line 23 (after 42.5 µs from the falling edge of HSYNC) is available for the insertion of video. WSS data transmission on Line 23 can be enabled using Subaddress 0x99, Bit 7. It is possible to blank the WSS portion of Line 23 with Subaddress 0xA1, Bit 7.
ADV7390/ADV7391/ADV7392/ADV7393 Data Sheet SD CLOSED CAPTIONING The ADV7390/ADV7391/ADV7392/ADV7393 automatically generate all clock run-in signals and timing that support closed captioning on Line 21 and Line 284. All pixels inputs are ignored on Line 21 and Line 284 if closed captioning is enabled. Subaddress 0x91 to Subaddress 0x94 The ADV7390/ADV7391/ADV7392/ADV7393 support closed captioning conforming to the standard television synchronizing waveform for color trans-mission.
Data Sheet ADV7390/ADV7391/ADV7392/ADV7393 INTERNAL TEST PATTERN GENERATION SD TEST PATTERNS ED/HD TEST PATTERNS The ADV7390/ADV7391/ADV7392/ADV7393 are able to internally generate SD color bar and black bar test patterns. For this function, a 27 MHz clock signal must be applied to the CLKIN pin. The ADV7390/ADV7391/ADV7392/ADV7393 are able to internally generate ED/HD color bar, black bar, and hatch test patterns. For ED test patterns, a 27 MHz clock signal must be applied to the CLKIN pin.
ADV7390/ADV7391/ADV7392/ADV7393 Data Sheet SD TIMING Mode 0 (CCIR-656)—Slave Option (Subaddress 0x8A = X X X X X 0 0 0) The ADV7390/ADV7391/ADV7392/ADV7393 are controlled by the SAV (start of active video) and EAV (end of active video) time codes embedded in the pixel data. All timing information is transmitted using a 4-byte synchronization pattern. A synchronization pattern is sent immediately before and after each line during active picture and retrace.
Data Sheet ADV7390/ADV7391/ADV7392/ADV7393 DISPLAY DISPLAY VERTICAL BLANK 622 623 624 625 1 2 4 3 5 6 21 7 22 23 H ODD FIELD EVEN FIELD F DISPLAY DISPLAY VERTICAL BLANK 309 310 311 312 314 313 315 316 318 317 319 335 334 320 336 ODD FIELD F 06234-104 H EVEN FIELD Figure 106. SD Timing Mode 0, Master Option, PAL ANALOG VIDEO 06234-105 H F Figure 107.
ADV7390/ADV7391/ADV7392/ADV7393 DISPLAY DISPLAY 622 623 Data Sheet VERTICAL BLANK 624 625 1 2 4 3 5 6 7 23 22 21 HSYNC FIELD EVEN FIELD ODD FIELD DISPLAY DISPLAY 309 310 VERTICAL BLANK 311 312 313 314 315 316 317 318 319 320 334 335 336 ODD FIELD FIELD 06234-107 HSYNC EVEN FIELD Figure 109.
Data Sheet ADV7390/ADV7391/ADV7392/ADV7393 DISPLAY 522 DISPLAY VERTICAL BLANK 523 524 525 1 4 3 2 5 7 6 8 10 9 20 11 21 22 HSYNC VSYNC ODD FIELD EVEN FIELD DISPLAY DISPLAY VERTICAL BLANK 260 261 262 263 264 265 266 267 268 269 270 271 272 273 283 274 284 285 VSYNC 06234-109 HSYNC EVEN FIELD ODD FIELD Figure 111.
ADV7390/ADV7391/ADV7392/ADV7393 Data Sheet HSYNC VSYNC PAL = 864 × CLOCK/2 NTSC = 858 × CLOCK/2 PIXEL DATA Cb Y Cr Cb 06234-112 Y PAL = 132 × CLOCK/2 NTSC = 122 × CLOCK/2 Figure 114. SD Timing Mode 2, Odd-to-Even Field Transition (Master/Slave) Mode 3—Master/Slave Option (Subaddress 0x8A = X X X X X 1 1 0 or X X X X X 1 1 1) In this mode, the ADV7390/ADV7391/ADV7392/ADV7393 accept or generates horizontal synchronization and odd/even field signals.
Data Sheet ADV7390/ADV7391/ADV7392/ADV7393 HD TIMING DISPLAY FIELD 1 VERTICAL BLANKING INTERVAL 1124 1125 1 2 3 4 5 6 7 8 20 21 22 560 VSYNC HSYNC DISPLAY VERTICAL BLANKING INTERVAL FIELD 2 561 562 563 564 565 566 567 568 569 570 583 584 585 1123 06234-115 VSYNC HSYNC Figure 117. 1080i HSYNC and VSYNC Input Timing Rev. J | Page 85 of 107 Downloaded from Arrow.com.
ADV7390/ADV7391/ADV7392/ADV7393 Data Sheet VIDEO OUTPUT LEVELS SD YPrPb OUTPUT LEVELS—SMPTE/EBU N10 700mV BLACK BLUE RED MAGENTA GREEN CYAN YELLOW WHITE BLACK BLUE RED MAGENTA GREEN CYAN YELLOW WHITE Pattern: 100% Color Bars 700mV 300mV 06234-119 06234-116 300mV 700mV BLACK BLUE RED MAGENTA GREEN CYAN YELLOW WHITE BLACK Figure 121. Y Levels—PAL BLUE RED MAGENTA GREEN CYAN YELLOW WHITE Figure 118.
Data Sheet ADV7390/ADV7391/ADV7392/ADV7393 ED/HD YPrPb OUTPUT LEVELS INPUT CODE INPUT CODE EIA-770.2, STANDARD FOR Y OUTPUT VOLTAGE EIA-770.3, STANDARD FOR Y OUTPUT VOLTAGE 940 940 700mV 700mV 64 300mV 64 300mV EIA-770.3, STANDARD FOR Pr/Pb OUTPUT VOLTAGE 960 EIA-770.2, STANDARD FOR Pr/Pb OUTPUT VOLTAGE 960 600mV 512 700mV 06234-124 700mV 512 06234-122 64 64 Figure 126. EIA-770.3 Standard Output Signals (1080i/720p) Figure 124. EIA-770.
ADV7390/ADV7391/ADV7392/ADV7393 Data Sheet SD/ED/HD RGB OUTPUT LEVELS Pattern: 100%/75% Color Bars R R 700mV/525mV 700mV/525mV 300mV 300mV G G 700mV/525mV 700mV/525mV 300mV 300mV B B 06234-126 300mV 300mV Figure 128. SD/ED RGB Output Levels—RGB Sync Disabled 06234-128 700mV/525mV 700mV/525mV Figure 130.
Data Sheet ADV7390/ADV7391/ADV7392/ADV7393 SD OUTPUT PLOTS VOLTS VOLTS IRE:FLT 0.6 100 0.4 0.5 50 0.2 0 0 0 –0.2 10 L608 30 40 50 60 MICROSECONDS PRECISION MODE OFF APL = 44.5% SYNCHRONOUS SYNC =A 525 LINE NTSC µ FRAMES SELECTED 1, 2 SLOW CLAMP TO 0.00V AT 6.72µs 0 20 10 20 30 40 50 60 MICROSECONDS NOISE REDUCTION: 0.00dB PRECISION MODE OFF APL = 39.1% SYNCHRONOUS SOUND-IN-SYNC OFF 625 LINE NTSC NO FILTERING FRAMES SELECTED 1, 2, 3, 4 SLOW CLAMP TO 0.00 AT 6.72µs Figure 132.
ADV7390/ADV7391/ADV7392/ADV7393 Data Sheet VIDEO STANDARDS 0HDATUM SMPTE 274M ANALOG WAVEFORM DIGITAL HORIZONTAL BLANKING *1 272T 4T ANCILLARY DATA (OPTIONAL) OR BLANKING CODE EAV CODE 1920T DIGITAL ACTIVE LINE F 0 0 F C V b Y C r F 0 0 H* 0 0 F 0 0 V H* F F INPUT PIXELS 4T SAV CODE 4 CLOCK SAMPLE NUMBER 2112 C Y r 4 CLOCK 0 2199 2116 2156 44 188 192 2111 06234-136 FVH* = FVH AND PARITY BITS SAV/EAV: LINE 1–562: F = 0 SAV/EAV: LINE 563–1125: F = 1 SAV/EAV: LINE 1–20; 561–583; 1124–11
ADV7390/ADV7391/ADV7392/ADV7393 ACTIVE VIDEO 622 623 ACTIVE VIDEO VERTICAL BLANK 624 625 1 2 5 4 6 7 8 9 10 12 11 13 43 44 45 06234-139 Data Sheet Figure 141. ITU-R BT.1358 (625p) DISPLAY 747 748 749 4 3 2 1 750 7 6 5 8 25 26 27 744 745 06234-140 VERTICAL BLANKING INTERVAL Figure 142.
ADV7390/ADV7391/ADV7392/ADV7393 Data Sheet CONFIGURATION SCRIPTS The scripts listed in the following pages can be used to configure the ADV7390/ADV7391/ADV7392/ADV7393 for basic operation. Certain features are enabled by default. If required for a specific application, additional features can be enabled. Table 63 lists the scripts available for SD modes of operation. Similarly, Table 98 and Table 115 list the scripts available for ED and HD modes of operation, respectively.
Data Sheet ADV7390/ADV7391/ADV7392/ADV7393 Table 64. 8-Bit 525i YCrCb In (EAV/SAV), YPrPb Out Table 68. 8-Bit 525i YCrCb In, RGB Out Subaddress 0x17 0x00 0x01 0x80 Setting 0x02 0x1C 0x00 0x10 Subaddress 0x17 0x00 0x01 0x02 Setting 0x02 0x1C 0x00 0x10 0x80 0x10 0x82 0xC9 0x82 0xC9 0x8A 0x0C Description Software reset. All DACs enabled. PLL enabled (16×). SD input mode. NTSC standard. SSAF luma filter enabled. 1.3 MHz chroma filter enabled. Pixel data valid. YPrPb out.
ADV7390/ADV7391/ADV7392/ADV7393 Data Sheet Table 71. 10-Bit 525i YCrCb In, CVBS/Y-C Out Table 74. 16-Bit 525i YCrCb In, YPrPb Out Subaddress 0x17 0x00 0x01 0x80 Setting 0x02 0x1C 0x00 0x10 Subaddress 0x17 0x00 0x01 0x80 Setting 0x02 0x1C 0x00 0x10 0x82 0xCB 0x82 0xC9 0x88 0x8A 0x10 0x0C 0x88 0x8A 0x10 0x0C Description Software reset. All DACs enabled. PLL enabled (16×). SD input mode. NTSC standard. SSAF luma filter enabled. 1.3 MHz chroma filter enabled. Pixel data valid.
Data Sheet ADV7390/ADV7391/ADV7392/ADV7393 Table 77. 16-Bit 525i RGB In, CVBS/Y-C Out Subaddress 0x17 0x00 0x01 0x80 Setting 0x02 0x1C 0x00 0x10 0x82 0xCB 0x87 0x88 0x8A 0x80 0x10 0x0C Description Software reset. All DACs enabled. PLL enabled (16×). SD input mode. NTSC standard. SSAF luma filter enabled. 1.3 MHz chroma filter enabled. Pixel data valid. CVBS/Y-C (S-Video) out. SSAF PrPb filter enabled. Active video edge control enabled. Pedestal enabled. RGB input enabled. 16-bit RGB input enabled.
ADV7390/ADV7391/ADV7392/ADV7393 Data Sheet Table 83. 8-Bit 625i YCrCb In, YPrPb Out Table 87. 10-Bit 625i YCrCb In, YPrPb Out Subaddress 0x17 0x00 0x01 0x80 Setting 0x02 0x1C 0x00 0x11 Subaddress 0x17 0x00 0x01 0x80 Setting 0x02 0x1C 0x00 0x11 0x82 0xC1 0x82 0xC1 0x8A 0x0C 0x88 0x8A 0x10 0x0C Description Software reset. All DACs enabled. PLL enabled (16×). SD input mode. PAL standard. SSAF luma filter enabled. 1.3 MHz chroma filter enabled. Pixel data valid. YPrPb out.
Data Sheet ADV7390/ADV7391/ADV7392/ADV7393 Table 90. 10-Bit 625i YCrCb In, RGB Out Table 93. 16-Bit 625i RGB In, YPrPb Out Subaddress 0x17 0x00 0x01 0x02 Setting 0x02 0x1C 0x00 0x10 Subaddress 0x17 0x00 0x01 0x80 Setting 0x02 0x1C 0x00 0x11 0x80 0x11 0x82 0xC1 0x82 0xC1 0x87 0x88 0x8A 0x80 0x10 0x0C 0x88 0x8A 0x10 0x0C Description Software reset. All DACs enabled. PLL enabled (16×). SD input mode. RGB output enabled. RGB output sync enabled. PAL standard. SSAF luma filter enabled. 1.
ADV7390/ADV7391/ADV7392/ADV7393 Table 97. 16-Bit PAL Square Pixel RGB In, CVBS/Y-C Out Table 96. 8-Bit PAL Square Pixel YCrCb In (EAV/SAV), CVBS/Y-C Out Subaddress 0x17 0x00 0x01 0x80 Setting 0x02 0x1C 0x10 0x00 0x11 0x82 0xD3 0x8C 0x8D 0x8E 0x8F 0x0C 0x8C 0x79 0x26 Data Sheet Description Software reset. All DACs enabled. PLL enabled (16×). WLCSP required. SD input mode. PAL standard. SSAF luma filter enabled. 1.3 MHz chroma filter enabled. Pixel data valid. CVBS/Y-C (S-Video) out.
Data Sheet ADV7390/ADV7391/ADV7392/ADV7393 ENHANCED DEFINITION Table 98.
ADV7390/ADV7391/ADV7392/ADV7393 Data Sheet Table 105. 16-Bit 625p YCrCb In (EAV/SAV), RGB Out Table 109. 8-Bit 525p YCrCb In (EAV/SAV), RGB Out Subaddress 0x17 0x00 0x01 0x02 Setting 0x02 0x1C 0x10 0x10 Subaddress 0x17 0x00 0x01 Setting 0x02 0x1C 0x20 0x02 0x10 0x30 0x1C 0x30 0x04 0x31 0x01 0x31 0x01 Description Software reset. All DACs enabled. PLL enabled (8×). ED-SDR input mode. RGB output enabled. RGB output sync enabled. 625p at 50 Hz. EAV/SAV synchronization. EIA-770.2 output levels.
Data Sheet ADV7390/ADV7391/ADV7392/ADV7393 Table 113. 8-Bit 625p YCrCb In (EAV/SAV), RGB Out Table 114. 10-Bit 625p YCrCb In (EAV/SAV), RGB Out Subaddress 0x17 0x00 0x01 Setting 0x02 0x1C 0x20 Subaddress 0x17 0x00 0x01 Setting 0x02 0x1C 0x20 0x02 0x10 0x02 0x10 0x30 0x1C 0x30 0x1C 0x31 0x01 0x31 0x33 0x01 0x6C Description Software reset. All DACs enabled. PLL enabled (8×). ED-DDR input mode. Luma data clocked on falling edge of CLKIN. RGB output enabled. RGB output sync enabled.
ADV7390/ADV7391/ADV7392/ADV7393 Data Sheet Table 116. 16-Bit 720p YCrCb In (EAV/SAV), YPrPb Out Table 121. 16-Bit 1080i YCrCb In, YPrPb Out Subaddress 0x17 0x00 0x01 0x30 Setting 0x02 0x1C 0x10 0x2C Subaddress 0x17 0x00 0x01 0x30 Setting 0x02 0x1C 0x10 0x18 0x31 0x01 0x31 0x01 Description Software reset. All DACs enabled. PLL enabled (4×). HD-SDR input mode. 720p at 60 Hz/59.94 Hz. EAV/SAV synchronization. EIA-770.3 output levels. Pixel data valid. 4× oversampling. Description Software reset.
Data Sheet ADV7390/ADV7391/ADV7392/ADV7393 Table 126. 8-Bit 720p YCrCb In (EAV/SAV), RGB Out Table 129. 10-Bit 1080i YCrCb In (EAV/SAV), YPrPb Out Subaddress 0x17 0x00 0x01 Setting 0x02 0x1C 0x20 Subaddress 0x17 0x00 0x01 Setting 0x02 0x1C 0x20 0x02 0x10 0x30 0x6C 0x30 0x2C 0x31 0x33 0x01 0x6C 0x31 0x01 Description Software reset. All DACs enabled. PLL enabled (4×). HD-DDR input mode. Luma data clocked on falling edge of CLKIN. RGB output enabled. RGB output sync enabled. 720p at 60 Hz/59.
ADV7390/ADV7391/ADV7392/ADV7393 Data Sheet ADV7390/ADV7391/ADV7392/ADV7393 EVALUATION BOARD These two boards allow the user to perform a complete evaluation of the part, although it is also possible to order only the back-end board. Note that these two boards must be ordered separately. To accommodate evaluation of the ADV7390/ADV7391/ ADV7392/ADV7393, Analog Devices provides a two-board solution.
Data Sheet ADV7390/ADV7391/ADV7392/ADV7393 OUTLINE DIMENSIONS 5.10 5.00 SQ 4.90 0.60 MAX 0.60 MAX 25 32 24 4.75 BSC SQ PIN 1 INDICATOR 1 0.50 BSC 3.25 3.10 SQ 2.95 EXPOSED PAD 17 PKG-001050 SEATING PLANE 0.20 MIN BOTTOM VIEW 3.50 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF 0.30 0.25 0.18 9 11-10-2017-B 12° MAX 1.00 0.85 0.80 0.80 MAX 0.65 TYP 8 16 0.
ADV7390/ADV7391/ADV7392/ADV7393 Data Sheet 2.565 2.525 2.485 5 3 4 2 1 A BALL A1 IDENTIFIER B 3.045 3.005 2.965 2.50 REF C D E F 0.50 BALL PITCH TOP VIEW BOTTOM VIEW (BALL SIDE UP) (BALL SIDE DOWN) 0.660 0.600 0.540 0.390 0.360 0.330 SIDE VIEW 2.00 REF COPLANARITY 0.05 0.360 0.320 0.280 0.270 0.240 0.210 10-31-2012-C SEATING PLANE Figure 147. 30-Ball Wafer Level Chip Scale Package [WLCSP] (CB-30-3) Dimensions shown in millimeters DETAIL A (JEDEC 95) 0.30 0.23 0.18 31 40 30 0.
Data Sheet ADV7390/ADV7391/ADV7392/ADV7393 ORDERING GUIDE Model1, 2 ADV7390BCPZ ADV7390BCPZ-REEL ADV7390WBCPZ ADV7390WBCPZ-RL ADV7390BCBZ-A-RL ADV7391BCPZ ADV7391BCPZ-REEL ADV7391WBCPZ ADV7391WBCPZ-RL ADV7392BCPZ ADV7392BCPZ-REEL ADV7392BCPZ-3REEL ADV7392WBCPZ ADV7392WBCPZ-REEL ADV7393BCPZ ADV7393BCPZ-REEL ADV7393WBCPZ ADV7393WBCPZ-REEL EVAL-ADV739xFEZ EVAL-ADV7390EBZ EVAL-ADV7391EBZ EVAL-ADV7392EBZ EVAL-ADV7393EBZ 1 2 3 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +105°C −40°C to +105°C −40°