Datasheet

Data Sheet ADV7390/ADV7391/ADV7392/ADV7393
Rev. G | Page 101 of 108
Table 113. 8-Bit 625p YCrCb In (EAV/SAV), RGB Out
Subaddress Setting Description
0x17 0x02 Software reset.
0x00 0x1C All DACs enabled. PLL enabled (8×).
0x01 0x20 ED-DDR input mode. Luma data
clocked on falling edge of CLKIN.
0x02 0x10 RGB output enabled. RGB output sync
enabled.
0x30 0x1C 625p at 50 Hz. EAV/SAV synchroni-
zation. EIA-770.2 output levels.
0x31 0x01 Pixel data valid.
Table 114. 10-Bit 625p YCrCb In (EAV/SAV), RGB Out
Subaddress Setting Description
0x17 0x02 Software reset.
0x00 0x1C All DACs enabled. PLL enabled (8×).
0x01 0x20 ED-DDR input mode. Luma data
clocked on falling edge of CLKIN.
0x02 0x10 RGB output enabled. RGB output sync
enabled.
0x30 0x1C 625p at 50 Hz. EAV/SAV synchroni-
zation. EIA-770.2 output levels.
0x31 0x01 Pixel data valid.
0x33 0x6C 10-bit input enabled.
HIGH DEFINITION
Table 115. HD Configuration Scripts
Input Format
Input Data Width
Synchronization Format
Input Color Space
Output Color Space
Table Number
720p 8-bit DDR EAV/SAV YCrCb YPrPb Table 124
720p 8-bit DDR EAV/SAV YCrCb RGB Table 126
720p 10-bit DDR EAV/SAV YCrCb YPrPb Table 125
720p 10-bit DDR EAV/SAV YCrCb RGB Table 127
720p 16-bit SDR EAV/SAV YCrCb YPrPb Table 116
720p 16-bit SDR
HSYNC
/
VSYNC
YCrCb YPrPb Table 117
720p 16-bit SDR EAV/SAV YCrCb RGB Table 118
720p 16-bit SDR
HSYNC
/
VSYNC
YCrCb RGB Table 119
1080i 8-bit DDR EAV/SAV YCrCb YPrPb Table 128
1080i
8-bit DDR
EAV/SAV
YCrCb
RGB
Table 130
1080i 10-bit DDR EAV/SAV YCrCb YPrPb Table 129
1080i 10-bit DDR EAV/SAV YCrCb RGB Table 131
1080i 16-bit SDR EAV/SAV YCrCb YPrPb Table 120
1080i 16-bit SDR
HSYNC
/
VSYNC
YCrCb YPrPb Table 121
1080i 16-bit SDR EAV/SAV YCrCb RGB Table 122
1080i 16-bit SDR
HSYNC
/
VSYNC
YCrCb RGB Table 123