Datasheet

Data Sheet ADV7390/ADV7391/ADV7392/ADV7393
Rev. G | Page 13 of 108
Figure 6. SD Input, 16-Bit 4:4:4 RGB, Input Mode 000
Figure 7. ED/HD-SDR Input, 16-Bit 4:2:2 YCrCb, Input Mode 001
Figure 8. ED/HD-DDR Input, 8-/10-Bit 4:2:2 YCrCb (
HSYNC
/
VSYNC
), Input Mode 010
CONTROL
OUTPUTS
t
9
t
10
t
11
G0 G1 G2
B0 B1 B2
R0 R1 R2
t
12
t
14
t
13
PIXEL PORT
PIXEL PORT
PIXEL PORT
CLKIN
HSYNC
VSYNC
CONTROL
INPUTS
06234-004
CONTROL
OUTPUTS
PIXEL PORT
PIXEL PORT
Y0 Y1 Y2 Y3 Y4 Y5
Cr4Cb4Cr2Cb2Cr0Cb0
CLKIN
t
9
t
10
t
12
t
11
t
14
t
13
HSYNC
VSYNC
CONTROL
INPUTS
06234-005
CLKIN*
CONTROL
OUTPUTS
Cr2Y2Cb2Y1Cr0Y0Cb0
t
9
t
10
t
12
t
11
t
12
t
11
t
14
t
13
PIXEL PORT
HSYNC
VSYNC
CONTROL
INPUTS
*LUMA/CHROMA CLOCK RELATIONSHIP CAN BE INVERTED USING SUBADDRESS 0x01, BITS 1 AND 2.
06234-006