Datasheet

ADV7390/ADV7391/ADV7392/ADV7393 Data Sheet
Rev. G | Page 14 of 108
Figure 9. ED/HD-DDR Input, 8-/10-Bit 4:2:2 YCrCb (EAV/SAV), Input Mode 010
Figure 10. ED (at 54 MHz) Input, 8-/10-Bit 4:2:2 YCrCb (
HSYNC
/
VSYNC
), Input Mode 111
Figure 11. ED (at 54 MHz) Input, 8-/10-Bit 4:2:2 YCrCb (EAV/SAV), Input Mode 111
CONTROL
OUTPUTS
PIXEL PORT
*LUMA/CHROMA CLOCK RELATIONSHIP CAN BE INVERTED USING SUBADDRESS 0x01, BITS 1 AND 2.
Y1Cr0Y0Cb0XY00003FF
CLKIN*
t
9
t
10
t
12
t
11
t
12
t
11
t
14
t
13
06234-007
CLKIN
CONTROL
OUTPUTS
Y1Cr0Y0Cb0 Cr2
Y2
Cb2
t
9
t
10
t
12
t
11
t
13
t
14
PIXEL PORT
HSYNC
VSYNC
CONTROL
INPUTS
06234-008
CLKIN
CONTROL
OUTPUTS
3FF 00 00 XY Cb0 Y0 Cr0 Y1
PIXEL PORT
t
11
t
12
t
10
t
9
t
14
t
13
06234-009