Datasheet

ADV7390/ADV7391/ADV7392/ADV7393 Data Sheet

Rev. G | Page 50 of 108

DESIGN FEATURES

OUTPUT OVERSAMPLING

The ADV739x includes an on-chip phase-locked loop (PLL)

that allows for oversampling of SD, ED, and HD video data. By

default, the PLL is disabled. The PLL can be enabled using

Subaddress 0x00, Bit 1 = 0.

Table 40 shows the various oversampling rates supported in the

ADV739x.

External Sync Polarity

For SD and ED/HD modes, the ADV739x parts typically expect

HS and VS to be low during their respective blanking periods.

However, when the CEA861 compliance bit is enabled (0x39,

Bit 5 for ED/HD modes and 0x86, Bit 3 for SD modes), the part

expects the HS or VS to be active low or high depending on the

input format selected (0x30, Bits[7:3]).

If a different polarity other than the default is required for

ED/HD modes, 0x3A, Bits[2:0] can be used to invert PHSYNCB,

PVSYNCB or PBLANKB individually regardless of whether

CEA-861-B mode is enabled. It is not possible to invert

S_HSYNC or S_VSYNC.

Table 40. Output Oversampling Modes and Rates

Input Mode

(0x01, Bits[6:4])

PLL and Oversampling

Control (0x00, Bit 1)

SD/ED Oversample Rate

Select (0x0D, Bit 3)

HD Oversample Rate

Select (0x31, Bit 1)

Oversampling Mode

and Rate

000 SD 1 X X SD (2×)

000 SD 0 1 X SD (8×)

000 SD 0 0 X SD (16×)

001/010 ED 1 X X ED (1×)

001/010

ED (4×)

001/010 ED 0 0 X ED (8×)

001/010 HD 1 X X HD (1×)

001/010 HD 0 X 1 HD (2×)

001/010 HD 0 X 0 HD (4×)

111 ED (at 54 MHz) 1 X X ED (at 54 MHz) (1×)

111 ED (at 54 MHz) 0 1 X ED (at 54 MHz) (4×)

111 ED (at 54 MHz) 0 0 X ED (at 54 MHz) (8×)

X = don’t care