Datasheet

Data Sheet ADV7390/ADV7391/ADV7392/ADV7393
Rev. G | Page 53 of 108
is required. The active resolution is 640 × 480. For PAL
operation, an input clock of 29.5 MHz is required. The active
resolution is 768 × 576.
For CVBS and S-Video (Y-C) outputs, the SD subcarrier
frequency registers must be updated to reflect the input clock
frequency used in SD square pixel mode. The SD input standard
autodetection feature must be disabled in SD square pixel
mode. In square pixel mode, the timing diagrams shown in
Figure 64 and Figure 65 apply.
Figure 64. Square Pixel Mode EAV/SAV Embedded Timing
Figure 65. Square Pixel Mode Active Pixel Timing
Y
C
r
Y
F
F
0
0
0
0
X
Y
8
0
1
0
8
0
1
0
F
F
0
0
F
F
A
B
A
B
A
B
8
0
1
0
8
0
1
0
F
F
0
0
0
0
X
Y
C
b
Y
C
r
C
b
Y
C
b
Y
C
r
EAV CODE
SAV CODE
ANCILLARY DATA
(HANC)
4 CLOCK
4 CLOCK
272 CLOCK
1280 CLOCK
4 CLOCK
4 CLOCK
344 CLOCK
1536 CLOCK
END OF ACTIVE
VIDEO LINE
START OF ACTIVE
VIDEO LINE
ANALOG
VIDEO
INPUT PIXELS
NTSC/PAL M SYSTEM
(525 LINES/60Hz)
PAL SYSTEM
(625 LINES/50Hz)
Y
06234-065
FIELD
PIXEL
DATA
PAL = 308 CLOCK CYCLES
NTSC = 236 CLOCK CYCLES
Cb Y
Cr Y
HSYNC
06234-066